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target/xtensa: extract interrupt and exception helpers
Move helper functions related to interrupt and exception handling from op_helper.c and helper.c to exc_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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parent
8803bfea0e
commit
8d918d656a
4 changed files with 259 additions and 220 deletions
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@ -169,133 +169,6 @@ void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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}
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}
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#ifndef CONFIG_USER_ONLY
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static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
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{
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if (xtensa_option_enabled(env->config,
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XTENSA_OPTION_RELOCATABLE_VECTOR)) {
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return vector - env->config->vecbase + env->sregs[VECBASE];
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} else {
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return vector;
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}
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}
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/*!
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* Handle penging IRQ.
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* For the high priority interrupt jump to the corresponding interrupt vector.
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* For the level-1 interrupt convert it to either user, kernel or double
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* exception with the 'level-1 interrupt' exception cause.
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*/
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static void handle_interrupt(CPUXtensaState *env)
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{
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int level = env->pending_irq_level;
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if (level > xtensa_get_cintlevel(env) &&
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level <= env->config->nlevel &&
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(env->config->level_mask[level] &
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env->sregs[INTSET] &
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env->sregs[INTENABLE])) {
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CPUState *cs = CPU(xtensa_env_get_cpu(env));
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if (level > 1) {
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env->sregs[EPC1 + level - 1] = env->pc;
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env->sregs[EPS2 + level - 2] = env->sregs[PS];
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env->sregs[PS] =
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(env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
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env->pc = relocated_vector(env,
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env->config->interrupt_vector[level]);
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} else {
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env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
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if (env->sregs[PS] & PS_EXCM) {
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if (env->config->ndepc) {
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env->sregs[DEPC] = env->pc;
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} else {
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env->sregs[EPC1] = env->pc;
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}
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cs->exception_index = EXC_DOUBLE;
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} else {
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env->sregs[EPC1] = env->pc;
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cs->exception_index =
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(env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
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}
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env->sregs[PS] |= PS_EXCM;
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}
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env->exception_taken = 1;
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}
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}
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/* Called from cpu_handle_interrupt with BQL held */
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void xtensa_cpu_do_interrupt(CPUState *cs)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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if (cs->exception_index == EXC_IRQ) {
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qemu_log_mask(CPU_LOG_INT,
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"%s(EXC_IRQ) level = %d, cintlevel = %d, "
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"pc = %08x, a0 = %08x, ps = %08x, "
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"intset = %08x, intenable = %08x, "
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"ccount = %08x\n",
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__func__, env->pending_irq_level, xtensa_get_cintlevel(env),
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env->pc, env->regs[0], env->sregs[PS],
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env->sregs[INTSET], env->sregs[INTENABLE],
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env->sregs[CCOUNT]);
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handle_interrupt(env);
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}
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switch (cs->exception_index) {
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case EXC_WINDOW_OVERFLOW4:
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case EXC_WINDOW_UNDERFLOW4:
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case EXC_WINDOW_OVERFLOW8:
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case EXC_WINDOW_UNDERFLOW8:
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case EXC_WINDOW_OVERFLOW12:
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case EXC_WINDOW_UNDERFLOW12:
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case EXC_KERNEL:
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case EXC_USER:
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case EXC_DOUBLE:
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case EXC_DEBUG:
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qemu_log_mask(CPU_LOG_INT, "%s(%d) "
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"pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
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__func__, cs->exception_index,
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env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
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if (env->config->exception_vector[cs->exception_index]) {
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env->pc = relocated_vector(env,
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env->config->exception_vector[cs->exception_index]);
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env->exception_taken = 1;
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} else {
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qemu_log_mask(CPU_LOG_INT, "%s(pc = %08x) bad exception_index: %d\n",
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__func__, env->pc, cs->exception_index);
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}
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break;
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case EXC_IRQ:
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break;
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default:
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qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
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__func__, env->pc, cs->exception_index);
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break;
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}
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check_interrupts(env);
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}
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#else
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void xtensa_cpu_do_interrupt(CPUState *cs)
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{
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}
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#endif
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bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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cs->exception_index = EXC_IRQ;
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xtensa_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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#ifdef CONFIG_USER_ONLY
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int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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