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hw/ssi: Allwinner A10 SPI emulation

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This patch implements Allwinner A10 SPI controller emulation.
Only master-mode functionality is implemented.

Since U-Boot and Linux SPI drivers for Allwinner A10 perform only
byte-wide CPU access (no DMA) to the transmit and receive registers of
the peripheral, the emulated controller does not implement DMA control,
and supports only byte-wide access to transmit and receive registers
(half-word and word accesses will be treated as byte accesses).

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Message-id: 20241001221349.8319-2-strahinja.p.jankovic@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Strahinja Jankovic 2024-10-14 17:05:52 +01:00 • committed by Peter Maydell
parent 88446cfe06
commit 8d3dfb6205
5 changed files with 633 additions and 0 deletions
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57
include/hw/ssi/allwinner-a10-spi.h Normal file
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/*
* Allwinner SPI Bus Serial Interface registers definition
*
* Copyright (C) 2024 Strahinja Jankovic. <strahinja.p.jankovic@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef ALLWINNER_A10_SPI_H
#define ALLWINNER_A10_SPI_H
#include "hw/ssi/ssi.h"
#include "hw/sysbus.h"
#include "qemu/fifo8.h"
#include "qom/object.h"
/** Size of register I/O address space used by SPI device */
#define AW_A10_SPI_IOSIZE (0x1000)
/** Total number of known registers */
#define AW_A10_SPI_REGS_NUM (AW_A10_SPI_IOSIZE / sizeof(uint32_t))
#define AW_A10_SPI_FIFO_SIZE (64)
#define AW_A10_SPI_CS_LINES_NR (4)
#define TYPE_AW_A10_SPI "allwinner.spi"
OBJECT_DECLARE_SIMPLE_TYPE(AWA10SPIState, AW_A10_SPI)
struct AWA10SPIState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
SSIBus *bus;
qemu_irq irq;
qemu_irq cs_lines[AW_A10_SPI_CS_LINES_NR];
uint32_t regs[AW_A10_SPI_REGS_NUM];
Fifo8 rx_fifo;
Fifo8 tx_fifo;
};
#endif /* ALLWINNER_A10_SPI_H */