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Improvements for TARGET_PAGE_BITS_VARY
Fix for TCI ld16u_i64. Fix for segv on icount execute from i/o memory. Two misc cleanups. -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAl23AUwdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/nLwgAgp6uXYfxu5L5gyza tvAPieqn/Gyn9weNuJE6ZIgti9xmhVIz8V/EH5VabXBpwaWTs8ttDinjv05BgSUm p6Y0Zdbv6/oERA5KNtVuPMZXUpAyFL8w4bqtkwnlp7+0t7v1AtuNH09WqZ7B/VYG 0zMPic8n/gi9zRCnSBgToRXJrK9FBmVeJFjJEG42rLV7GBGBaTllFcWzT+EyoknO OigvZb6ZkNP+cAPZY4ELj2qrR+ziVMxyAMHxGQ4QiCx6QMAys+/Mf44Is8425h1/ GRKAEtfdUgptPMWLTQkivaH9l8pe71oj44NvCCSvfkPfynXAEyYsW+epCDWAmG71 sHbuFQ== =wSJn -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20191028' into staging Improvements for TARGET_PAGE_BITS_VARY Fix for TCI ld16u_i64. Fix for segv on icount execute from i/o memory. Two misc cleanups. # gpg: Signature made Mon 28 Oct 2019 14:55:08 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20191028: translate-all: Remove tb_alloc translate-all: fix uninitialized tb->orig_tb cputlb: Fix tlb_vaddr_to_host exec: Cache TARGET_PAGE_MASK for TARGET_PAGE_BITS_VARY exec: Promote TARGET_PAGE_MASK to target_long exec: Restrict TARGET_PAGE_BITS_VARY assert to CONFIG_DEBUG_TCG exec: Use const alias for TARGET_PAGE_BITS_VARY configure: Detect compiler support for __attribute__((alias)) exec: Split out variable page size support to exec-vary.c cpu: use ROUND_UP() to define xxx_PAGE_ALIGN cputlb: ensure _cmmu helper functions follow the naming standard tci: Add implementation for INDEX_op_ld16u_i64 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
8c68ff250a
12 changed files with 214 additions and 77 deletions
34
exec.c
34
exec.c
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@ -91,11 +91,6 @@ AddressSpace address_space_memory;
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static MemoryRegion io_mem_unassigned;
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#endif
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#ifdef TARGET_PAGE_BITS_VARY
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int target_page_bits;
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bool target_page_bits_decided;
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#endif
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CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
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/* current CPU in the current thread. It is only valid inside
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@ -109,37 +104,8 @@ int use_icount;
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uintptr_t qemu_host_page_size;
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intptr_t qemu_host_page_mask;
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bool set_preferred_target_page_bits(int bits)
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{
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/* The target page size is the lowest common denominator for all
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* the CPUs in the system, so we can only make it smaller, never
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* larger. And we can't make it smaller once we've committed to
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* a particular size.
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*/
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#ifdef TARGET_PAGE_BITS_VARY
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assert(bits >= TARGET_PAGE_BITS_MIN);
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if (target_page_bits == 0 || target_page_bits > bits) {
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if (target_page_bits_decided) {
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return false;
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}
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target_page_bits = bits;
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}
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#endif
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return true;
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}
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#if !defined(CONFIG_USER_ONLY)
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static void finalize_target_page_bits(void)
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{
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#ifdef TARGET_PAGE_BITS_VARY
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if (target_page_bits == 0) {
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target_page_bits = TARGET_PAGE_BITS_MIN;
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}
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target_page_bits_decided = true;
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#endif
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}
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typedef struct PhysPageEntry PhysPageEntry;
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struct PhysPageEntry {
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