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target/arm: Rename gen_exception_insn to gen_exception_insn_el

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-06-10 14:32:32 +01:00 • committed by Peter Maydell
parent 9c9d03f0c5
commit 8c5d24dc7d
6 changed files with 53 additions and 52 deletions
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39
target/arm/translate.c
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@ -1100,8 +1100,8 @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
s->base.is_jmp = DISAS_NORETURN;
}
void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
uint32_t syn, uint32_t target_el)
void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
uint32_t syn, uint32_t target_el)
{
gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el));
}
@ -1117,8 +1117,8 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
void unallocated_encoding(DisasContext *s)
{
/* Unallocated and reserved encodings are uncategorized */
gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
}
/* Force a TB lookup after an instruction that changes the CPU state. */
@ -2869,8 +2869,8 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
undef:
/* If we get here then some access check did not pass */
gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
syn_uncategorized(), exc_target);
gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
syn_uncategorized(), exc_target);
return false;
}
@ -5094,7 +5094,8 @@ static void gen_srs(DisasContext *s,
* For the UNPREDICTABLE cases we choose to UNDEF.
*/
if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) {
gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), 3);
gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
syn_uncategorized(), 3);
return;
}
@ -8479,8 +8480,8 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
* Do the check-and-raise-exception by hand.
*/
if (s->fp_excp_el) {
gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
syn_uncategorized(), s->fp_excp_el);
gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
syn_uncategorized(), s->fp_excp_el);
return true;
}
}
@ -8582,8 +8583,8 @@ static bool trans_LE(DisasContext *s, arg_LE *a)
tmp = load_cpu_field(v7m.ltpsize);
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc);
tcg_temp_free_i32(tmp);
gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
default_exception_el(s));
gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
default_exception_el(s));
gen_set_label(skipexc);
}
@ -9053,8 +9054,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
* UsageFault exception.
*/
if (arm_dc_feature(s, ARM_FEATURE_M)) {
gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
default_exception_el(s));
gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
default_exception_el(s));
return;
}
@ -9063,8 +9064,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
* Illegal execution state. This has priority over BTI
* exceptions, but comes after instruction abort exceptions.
*/
gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
syn_illegalstate(), default_exception_el(s));
gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
syn_illegalstate(), default_exception_el(s));
return;
}
@ -9633,8 +9634,8 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
* Illegal execution state. This has priority over BTI
* exceptions, but comes after instruction abort exceptions.
*/
gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF,
syn_illegalstate(), default_exception_el(dc));
gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF,
syn_illegalstate(), default_exception_el(dc));
return;
}
@ -9707,8 +9708,8 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
*/
tcg_remove_ops_after(dc->insn_eci_rewind);
dc->condjmp = 0;
gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
default_exception_el(dc));
gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
default_exception_el(dc));
}
arm_post_translate_insn(dc);