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trivial patches for 2015-10-08
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJWFp75AAoJEL7lnXSkw9fbImgIALGEo20bKy2X624iPgTePuPb e34TjoRoB7s3rZ2SrVCIZCAsSKPtt+qQcGmJxt1YUtW0yD32aDJWQ3mm7EQTtjc+ 6dNZF5eI0322YPMePzAb1SvEc+T4b1otUS/wxENnA4D8s0lBVn1L47Ajt2E8/SP7 rv0XTUnzwc5s4qjNNUqidvrSvmYqj5DhMh3veSb+FDm3DSKlB3Z1eq3yx0+g2ghR zsa2cUnX/6y26paeMqCMiFOAWSqQa80TBjgDyRiul2jrPeaM/As2Cr657MKugvi9 4vMg9CqmLiwerTkicv5kOsUFAetdLCuvnqNqol3DFRxJ+4bbOp3VQccrBXWtZY0= =QRsk -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mjt/tags/pull-trivial-patches-2015-10-08' into staging trivial patches for 2015-10-08 # gpg: Signature made Thu 08 Oct 2015 17:51:05 BST using RSA key ID A4C3D7DB # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" * remotes/mjt/tags/pull-trivial-patches-2015-10-08: tests: Unique test path for /string-visitor/output linux-user: Remove type casts to union type linux-user: Use g_new() & friends where that makes obvious sense rocker: Use g_new() & friends where that makes obvious sense .travis.yml: Run make check for all targets, not just some hw: char: Remove unnecessary variable hw: timer: Remove unnecessary variable qapi: add missing @ MAINTAINERS: Add NSIS file for W32, W64 hosts target-ppc: Remove unnecessary variable target-microblaze: Remove unnecessary variable s/cpu_get_real_ticks/cpu_get_host_ticks/ pc: check for underflow in load_linux pci-assign: do not include sys/io.h block/ssh: remove dead code imx_serial: Generate interrupt on tx empty if enabled sdhci: Change debug prints to compile unconditionally sdhci: use PRIx64 for uint64_t type Add .dir-locals.el file to configure emacs coding style Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
8be6e623a2
27 changed files with 83 additions and 91 deletions
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@ -182,15 +182,13 @@ static void serial_receive(void *opaque, const uint8_t *buf, int size)
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static int serial_can_receive(void *opaque)
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{
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ETRAXSerial *s = opaque;
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int r;
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/* Is the receiver enabled? */
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if (!(s->regs[RW_REC_CTRL] & (1 << 3))) {
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return 0;
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}
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r = sizeof(s->rx_fifo) - s->rx_fifo_len;
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return r;
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return sizeof(s->rx_fifo) - s->rx_fifo_len;
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}
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static void serial_event(void *opaque, int event)
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@ -66,7 +66,9 @@ static void imx_update(IMXSerialState *s)
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uint32_t flags;
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flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
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if (!(s->ucr1 & UCR1_TXMPTYEN)) {
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if (s->ucr1 & UCR1_TXMPTYEN) {
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flags |= (s->uts1 & UTS1_TXEMPTY);
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} else {
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flags &= ~USR1_TRDY;
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}
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@ -22,7 +22,6 @@
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*/
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#include <stdio.h>
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#include <unistd.h>
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#include <sys/io.h>
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#include <sys/mman.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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@ -985,6 +985,10 @@ static void load_linux(PCMachineState *pcms,
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setup_size = 4;
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}
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setup_size = (setup_size+1)*512;
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if (setup_size > kernel_size) {
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fprintf(stderr, "qemu: invalid kernel header\n");
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exit(1);
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}
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kernel_size -= setup_size;
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setup = g_malloc(setup_size);
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@ -848,7 +848,7 @@ static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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uint32_t xirr = icp_accept(ss);
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args[0] = xirr;
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args[1] = cpu_get_real_ticks();
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args[1] = cpu_get_host_ticks();
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return H_SUCCESS;
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}
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@ -1362,7 +1362,7 @@ static int pci_rocker_init(PCIDevice *dev)
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r->fp_ports = ROCKER_FP_PORTS_MAX;
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}
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r->rings = g_malloc(sizeof(DescRing *) * rocker_pci_ring_count(r));
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r->rings = g_new(DescRing *, rocker_pci_ring_count(r));
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if (!r->rings) {
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goto err_rings_alloc;
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}
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@ -142,7 +142,7 @@ bool desc_ring_set_size(DescRing *ring, uint32_t size)
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ring->size = size;
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ring->head = ring->tail = 0;
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ring->info = g_realloc(ring->info, size * sizeof(DescInfo));
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ring->info = g_renew(DescInfo, ring->info, size);
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if (!ring->info) {
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return false;
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}
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@ -345,7 +345,7 @@ DescRing *desc_ring_alloc(Rocker *r, int index)
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{
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DescRing *ring;
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ring = g_malloc0(sizeof(DescRing));
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ring = g_new0(DescRing, 1);
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if (!ring) {
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return NULL;
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}
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@ -218,7 +218,7 @@ FpPort *fp_port_alloc(Rocker *r, char *sw_name,
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MACAddr *start_mac, unsigned int index,
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NICPeers *peers)
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{
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FpPort *port = g_malloc0(sizeof(FpPort));
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FpPort *port = g_new0(FpPort, 1);
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if (!port) {
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return NULL;
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@ -367,7 +367,7 @@ static OfDpaFlow *of_dpa_flow_alloc(uint64_t cookie)
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OfDpaFlow *flow;
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int64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) / 1000;
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flow = g_malloc0(sizeof(OfDpaFlow));
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flow = g_new0(OfDpaFlow, 1);
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if (!flow) {
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return NULL;
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}
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@ -811,7 +811,7 @@ static int of_dpa_group_get_stats(OfDpa *of_dpa, uint32_t id)
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static OfDpaGroup *of_dpa_group_alloc(uint32_t id)
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{
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OfDpaGroup *group = g_malloc0(sizeof(OfDpaGroup));
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OfDpaGroup *group = g_new0(OfDpaGroup, 1);
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if (!group) {
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return NULL;
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@ -2039,15 +2039,14 @@ static int of_dpa_cmd_add_l2_flood(OfDpa *of_dpa, OfDpaGroup *group,
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group->l2_flood.group_count =
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rocker_tlv_get_le16(group_tlvs[ROCKER_TLV_OF_DPA_GROUP_COUNT]);
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tlvs = g_malloc0((group->l2_flood.group_count + 1) *
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sizeof(RockerTlv *));
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tlvs = g_new0(RockerTlv *, group->l2_flood.group_count + 1);
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if (!tlvs) {
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return -ROCKER_ENOMEM;
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}
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g_free(group->l2_flood.group_ids);
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group->l2_flood.group_ids =
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g_malloc0(group->l2_flood.group_count * sizeof(uint32_t));
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g_new0(uint32_t, group->l2_flood.group_count);
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if (!group->l2_flood.group_ids) {
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err = -ROCKER_ENOMEM;
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goto err_out;
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@ -834,7 +834,7 @@ static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
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static void timebase_pre_save(void *opaque)
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{
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PPCTimebase *tb = opaque;
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uint64_t ticks = cpu_get_real_ticks();
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uint64_t ticks = cpu_get_host_ticks();
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PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
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if (!first_ppc_cpu->env.tb_env) {
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@ -878,7 +878,7 @@ static int timebase_post_load(void *opaque, int version_id)
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NANOSECONDS_PER_SECOND);
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guest_tb = tb_remote->guest_timebase + MIN(0, migration_duration_tb);
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tb_off_adj = guest_tb - cpu_get_real_ticks();
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tb_off_adj = guest_tb - cpu_get_host_ticks();
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tb_off = first_ppc_cpu->env.tb_env->tb_offset;
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trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off,
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@ -22,6 +22,7 @@
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <inttypes.h>
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#include "hw/hw.h"
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#include "sysemu/block-backend.h"
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#include "sysemu/blockdev.h"
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@ -36,24 +37,24 @@
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#define SDHC_DEBUG 0
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#endif
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#if SDHC_DEBUG == 0
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#define DPRINT_L1(fmt, args...) do { } while (0)
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#define DPRINT_L2(fmt, args...) do { } while (0)
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#define ERRPRINT(fmt, args...) do { } while (0)
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#elif SDHC_DEBUG == 1
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#define DPRINT_L1(fmt, args...) \
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do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0)
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#define DPRINT_L2(fmt, args...) do { } while (0)
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#define ERRPRINT(fmt, args...) \
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do {fprintf(stderr, "QEMU SDHC ERROR: "fmt, ## args); } while (0)
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#else
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#define DPRINT_L1(fmt, args...) \
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do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0)
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#define DPRINT_L2(fmt, args...) \
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do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0)
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#define ERRPRINT(fmt, args...) \
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do {fprintf(stderr, "QEMU SDHC ERROR: "fmt, ## args); } while (0)
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#endif
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#define DPRINT_L1(fmt, args...) \
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do { \
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if (SDHC_DEBUG) { \
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fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
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} \
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} while (0)
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#define DPRINT_L2(fmt, args...) \
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do { \
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if (SDHC_DEBUG > 1) { \
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fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
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} \
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} while (0)
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#define ERRPRINT(fmt, args...) \
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do { \
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if (SDHC_DEBUG) { \
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fprintf(stderr, "QEMU SDHC ERROR: " fmt, ## args); \
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} \
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} while (0)
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/* Default SD/MMC host controller features information, which will be
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* presented in CAPABILITIES register of generic SD host controller at reset.
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break;
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case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */
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s->admasysaddr = dscr.addr;
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DPRINT_L1("ADMA link: admasysaddr=0x%lx\n", s->admasysaddr);
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DPRINT_L1("ADMA link: admasysaddr=0x%" PRIx64 "\n",
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s->admasysaddr);
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break;
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default:
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s->admasysaddr += dscr.incr;
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}
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if (dscr.attr & SDHC_ADMA_ATTR_INT) {
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DPRINT_L1("ADMA interrupt: admasysaddr=0x%lx\n", s->admasysaddr);
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DPRINT_L1("ADMA interrupt: admasysaddr=0x%" PRIx64 "\n",
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s->admasysaddr);
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if (s->norintstsen & SDHC_NISEN_DMA) {
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s->norintsts |= SDHC_NIS_DMA;
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}
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@ -590,10 +590,8 @@ static void nvram_writel (void *opaque, hwaddr addr, uint32_t value)
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static uint32_t nvram_readb (void *opaque, hwaddr addr)
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{
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M48t59State *NVRAM = opaque;
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uint32_t retval;
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retval = m48t59_read(NVRAM, addr);
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return retval;
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return m48t59_read(NVRAM, addr);
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}
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static uint32_t nvram_readw (void *opaque, hwaddr addr)
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