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hw/riscv: sifive_u: Hook a GPIO controller

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SiFive FU540 SoC integrates a GPIO controller with 16 GPIO lines.
This hooks the exsiting SiFive GPIO model to the SoC, and adds its
device tree data as well.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-8-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2020-06-08 07:17:36 -07:00 • committed by Alistair Francis
parent 4bb216f637
commit 8a88b9f54f
2 changed files with 60 additions and 2 deletions
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19
include/hw/riscv/sifive_u.h
View file

@ -22,6 +22,7 @@
#include "hw/net/cadence_gem.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
#include "hw/riscv/sifive_gpio.h"
#include "hw/riscv/sifive_u_prci.h"
#include "hw/riscv/sifive_u_otp.h"
@ -40,6 +41,7 @@ typedef struct SiFiveUSoCState {
RISCVHartArrayState u_cpus;
DeviceState *plic;
SiFiveUPRCIState prci;
SIFIVEGPIOState gpio;
SiFiveUOTPState otp;
CadenceGEMState gem;
@ -73,6 +75,7 @@ enum {
SIFIVE_U_PRCI,
SIFIVE_U_UART0,
SIFIVE_U_UART1,
SIFIVE_U_GPIO,
SIFIVE_U_OTP,
SIFIVE_U_FLASH0,
SIFIVE_U_DRAM,
@ -83,6 +86,22 @@ enum {
enum {
SIFIVE_U_UART0_IRQ = 4,
SIFIVE_U_UART1_IRQ = 5,
SIFIVE_U_GPIO_IRQ0 = 7,
SIFIVE_U_GPIO_IRQ1 = 8,
SIFIVE_U_GPIO_IRQ2 = 9,
SIFIVE_U_GPIO_IRQ3 = 10,
SIFIVE_U_GPIO_IRQ4 = 11,
SIFIVE_U_GPIO_IRQ5 = 12,
SIFIVE_U_GPIO_IRQ6 = 13,
SIFIVE_U_GPIO_IRQ7 = 14,
SIFIVE_U_GPIO_IRQ8 = 15,
SIFIVE_U_GPIO_IRQ9 = 16,
SIFIVE_U_GPIO_IRQ10 = 17,
SIFIVE_U_GPIO_IRQ11 = 18,
SIFIVE_U_GPIO_IRQ12 = 19,
SIFIVE_U_GPIO_IRQ13 = 20,
SIFIVE_U_GPIO_IRQ14 = 21,
SIFIVE_U_GPIO_IRQ15 = 22,
SIFIVE_U_GEM_IRQ = 0x35
};