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target/ppc: Implement gathering irq statistics

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Count exceptions which can be queried with info irq monitor command.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230606220200.7EBCC74635C@zero.eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
BALATON Zoltan 2023-06-07 00:02:00 +02:00 • committed by Daniel Henrique Barboza
parent 12cae32fe1
commit 8a15ccee4d
3 changed files with 20 additions and 0 deletions
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1
target/ppc/cpu.h
View file

@ -1195,6 +1195,7 @@ struct CPUArchState {
int error_code; int error_code;
uint32_t pending_interrupts; uint32_t pending_interrupts;
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
uint64_t excp_stats[POWERPC_EXCP_NB];
/* /*
* This is the IRQ controller, which is implementation dependent and only * This is the IRQ controller, which is implementation dependent and only
* relevant when emulating a complete machine. Note that this isn't used * relevant when emulating a complete machine. Note that this isn't used

18
target/ppc/cpu_init.c
View file

@ -48,6 +48,7 @@
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
#include "hw/boards.h" #include "hw/boards.h"
#include "hw/intc/intc.h"
#endif #endif
/* #define PPC_DEBUG_SPR */ /* #define PPC_DEBUG_SPR */
@ -7123,6 +7124,16 @@ static bool ppc_cpu_is_big_endian(CPUState *cs)
return !FIELD_EX64(env->msr, MSR, LE); return !FIELD_EX64(env->msr, MSR, LE);
} }
static bool ppc_get_irq_stats(InterruptStatsProvider *obj,
uint64_t **irq_counts, unsigned int *nb_irqs)
{
CPUPPCState *env = &POWERPC_CPU(obj)->env;
*irq_counts = env->excp_stats;
*nb_irqs = ARRAY_SIZE(env->excp_stats);
return true;
}
#ifdef CONFIG_TCG #ifdef CONFIG_TCG
static void ppc_cpu_exec_enter(CPUState *cs) static void ppc_cpu_exec_enter(CPUState *cs)
{ {
@ -7286,6 +7297,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = ppc_cpu_gdb_write_register; cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &ppc_sysemu_ops; cc->sysemu_ops = &ppc_sysemu_ops;
INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics = ppc_get_irq_stats;
#endif #endif
cc->gdb_num_core_regs = 71; cc->gdb_num_core_regs = 71;
@ -7323,6 +7335,12 @@ static const TypeInfo ppc_cpu_type_info = {
.abstract = true, .abstract = true,
.class_size = sizeof(PowerPCCPUClass), .class_size = sizeof(PowerPCCPUClass),
.class_init = ppc_cpu_class_init, .class_init = ppc_cpu_class_init,
#ifndef CONFIG_USER_ONLY
.interfaces = (InterfaceInfo[]) {
{ TYPE_INTERRUPT_STATS_PROVIDER },
{ }
},
#endif
}; };
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY

1
target/ppc/excp_helper.c
View file

@ -1655,6 +1655,7 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
" => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp), " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
excp, env->error_code); excp, env->error_code);
env->excp_stats[excp]++;
switch (env->excp_model) { switch (env->excp_model) {
case POWERPC_EXCP_40x: case POWERPC_EXCP_40x: