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target/arm: Create gen_gvec_{sri,sli}
The functions eliminate duplication of the special cases for this operation. They match up with the GVecGen2iFn typedef. Add out-of-line helpers. We got away with only having inline expanders because the neon vector size is only 16 bytes, and we know that the inline expansion will always succeed. When we reuse this for SVE, tcg-gvec-op may decide to use an out-of-line helper due to longer vector lengths. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200513163245.17915-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
6ccd48d4ea
commit
893ab0542a
5 changed files with 160 additions and 101 deletions
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@ -4454,47 +4454,62 @@ static void gen_shr64_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
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static void gen_shr_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
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{
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if (sh == 0) {
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tcg_gen_mov_vec(d, a);
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} else {
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TCGv_vec t = tcg_temp_new_vec_matching(d);
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TCGv_vec m = tcg_temp_new_vec_matching(d);
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TCGv_vec t = tcg_temp_new_vec_matching(d);
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TCGv_vec m = tcg_temp_new_vec_matching(d);
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tcg_gen_dupi_vec(vece, m, MAKE_64BIT_MASK((8 << vece) - sh, sh));
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tcg_gen_shri_vec(vece, t, a, sh);
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tcg_gen_and_vec(vece, d, d, m);
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tcg_gen_or_vec(vece, d, d, t);
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tcg_gen_dupi_vec(vece, m, MAKE_64BIT_MASK((8 << vece) - sh, sh));
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tcg_gen_shri_vec(vece, t, a, sh);
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tcg_gen_and_vec(vece, d, d, m);
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tcg_gen_or_vec(vece, d, d, t);
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tcg_temp_free_vec(t);
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tcg_temp_free_vec(m);
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}
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tcg_temp_free_vec(t);
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tcg_temp_free_vec(m);
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}
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static const TCGOpcode vecop_list_sri[] = { INDEX_op_shri_vec, 0 };
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void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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int64_t shift, uint32_t opr_sz, uint32_t max_sz)
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{
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static const TCGOpcode vecop_list[] = { INDEX_op_shri_vec, 0 };
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const GVecGen2i ops[4] = {
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{ .fni8 = gen_shr8_ins_i64,
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.fniv = gen_shr_ins_vec,
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.fno = gen_helper_gvec_sri_b,
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.load_dest = true,
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.opt_opc = vecop_list,
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.vece = MO_8 },
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{ .fni8 = gen_shr16_ins_i64,
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.fniv = gen_shr_ins_vec,
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.fno = gen_helper_gvec_sri_h,
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.load_dest = true,
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.opt_opc = vecop_list,
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.vece = MO_16 },
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{ .fni4 = gen_shr32_ins_i32,
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.fniv = gen_shr_ins_vec,
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.fno = gen_helper_gvec_sri_s,
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.load_dest = true,
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.opt_opc = vecop_list,
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.vece = MO_32 },
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{ .fni8 = gen_shr64_ins_i64,
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.fniv = gen_shr_ins_vec,
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.fno = gen_helper_gvec_sri_d,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true,
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.opt_opc = vecop_list,
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.vece = MO_64 },
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};
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const GVecGen2i sri_op[4] = {
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{ .fni8 = gen_shr8_ins_i64,
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.fniv = gen_shr_ins_vec,
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.load_dest = true,
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.opt_opc = vecop_list_sri,
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.vece = MO_8 },
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{ .fni8 = gen_shr16_ins_i64,
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.fniv = gen_shr_ins_vec,
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.load_dest = true,
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.opt_opc = vecop_list_sri,
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.vece = MO_16 },
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{ .fni4 = gen_shr32_ins_i32,
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.fniv = gen_shr_ins_vec,
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.load_dest = true,
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.opt_opc = vecop_list_sri,
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.vece = MO_32 },
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{ .fni8 = gen_shr64_ins_i64,
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.fniv = gen_shr_ins_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true,
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.opt_opc = vecop_list_sri,
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.vece = MO_64 },
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};
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/* tszimm encoding produces immediates in the range [1..esize]. */
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tcg_debug_assert(shift > 0);
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tcg_debug_assert(shift <= (8 << vece));
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/* Shift of esize leaves destination unchanged. */
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if (shift < (8 << vece)) {
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tcg_gen_gvec_2i(rd_ofs, rm_ofs, opr_sz, max_sz, shift, &ops[vece]);
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} else {
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/* Nop, but we do need to clear the tail. */
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tcg_gen_gvec_mov(vece, rd_ofs, rd_ofs, opr_sz, max_sz);
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}
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}
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static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
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{
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@ -4532,47 +4547,60 @@ static void gen_shl64_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
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static void gen_shl_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
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{
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if (sh == 0) {
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tcg_gen_mov_vec(d, a);
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} else {
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TCGv_vec t = tcg_temp_new_vec_matching(d);
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TCGv_vec m = tcg_temp_new_vec_matching(d);
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TCGv_vec t = tcg_temp_new_vec_matching(d);
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TCGv_vec m = tcg_temp_new_vec_matching(d);
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tcg_gen_dupi_vec(vece, m, MAKE_64BIT_MASK(0, sh));
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tcg_gen_shli_vec(vece, t, a, sh);
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tcg_gen_and_vec(vece, d, d, m);
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tcg_gen_or_vec(vece, d, d, t);
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tcg_gen_shli_vec(vece, t, a, sh);
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tcg_gen_dupi_vec(vece, m, MAKE_64BIT_MASK(0, sh));
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tcg_gen_and_vec(vece, d, d, m);
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tcg_gen_or_vec(vece, d, d, t);
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tcg_temp_free_vec(t);
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tcg_temp_free_vec(m);
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}
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tcg_temp_free_vec(t);
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tcg_temp_free_vec(m);
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}
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static const TCGOpcode vecop_list_sli[] = { INDEX_op_shli_vec, 0 };
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void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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int64_t shift, uint32_t opr_sz, uint32_t max_sz)
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{
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static const TCGOpcode vecop_list[] = { INDEX_op_shli_vec, 0 };
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const GVecGen2i ops[4] = {
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{ .fni8 = gen_shl8_ins_i64,
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.fniv = gen_shl_ins_vec,
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.fno = gen_helper_gvec_sli_b,
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.load_dest = true,
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.opt_opc = vecop_list,
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.vece = MO_8 },
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{ .fni8 = gen_shl16_ins_i64,
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.fniv = gen_shl_ins_vec,
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.fno = gen_helper_gvec_sli_h,
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.load_dest = true,
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.opt_opc = vecop_list,
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.vece = MO_16 },
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{ .fni4 = gen_shl32_ins_i32,
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.fniv = gen_shl_ins_vec,
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.fno = gen_helper_gvec_sli_s,
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.load_dest = true,
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.opt_opc = vecop_list,
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.vece = MO_32 },
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{ .fni8 = gen_shl64_ins_i64,
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.fniv = gen_shl_ins_vec,
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.fno = gen_helper_gvec_sli_d,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true,
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.opt_opc = vecop_list,
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.vece = MO_64 },
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};
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const GVecGen2i sli_op[4] = {
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{ .fni8 = gen_shl8_ins_i64,
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.fniv = gen_shl_ins_vec,
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.load_dest = true,
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.opt_opc = vecop_list_sli,
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.vece = MO_8 },
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{ .fni8 = gen_shl16_ins_i64,
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.fniv = gen_shl_ins_vec,
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.load_dest = true,
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.opt_opc = vecop_list_sli,
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.vece = MO_16 },
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{ .fni4 = gen_shl32_ins_i32,
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.fniv = gen_shl_ins_vec,
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.load_dest = true,
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.opt_opc = vecop_list_sli,
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.vece = MO_32 },
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{ .fni8 = gen_shl64_ins_i64,
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.fniv = gen_shl_ins_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true,
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.opt_opc = vecop_list_sli,
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.vece = MO_64 },
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};
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/* tszimm encoding produces immediates in the range [0..esize-1]. */
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tcg_debug_assert(shift >= 0);
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tcg_debug_assert(shift < (8 << vece));
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if (shift == 0) {
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tcg_gen_gvec_mov(vece, rd_ofs, rm_ofs, opr_sz, max_sz);
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} else {
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tcg_gen_gvec_2i(rd_ofs, rm_ofs, opr_sz, max_sz, shift, &ops[vece]);
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}
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}
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static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
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{
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@ -5715,20 +5743,14 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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}
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/* Right shift comes here negative. */
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shift = -shift;
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/* Shift out of range leaves destination unchanged. */
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if (shift < 8 << size) {
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tcg_gen_gvec_2i(rd_ofs, rm_ofs, vec_size, vec_size,
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shift, &sri_op[size]);
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}
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gen_gvec_sri(size, rd_ofs, rm_ofs, shift,
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vec_size, vec_size);
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return 0;
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case 5: /* VSHL, VSLI */
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if (u) { /* VSLI */
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/* Shift out of range leaves destination unchanged. */
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if (shift < 8 << size) {
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tcg_gen_gvec_2i(rd_ofs, rm_ofs, vec_size,
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vec_size, shift, &sli_op[size]);
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}
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gen_gvec_sli(size, rd_ofs, rm_ofs, shift,
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vec_size, vec_size);
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} else { /* VSHL */
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/* Shifts larger than the element size are
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* architecturally valid and results in zero.
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