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hw/nvme: move nvme emulation out of hw/block
With the introduction of the nvme-subsystem device we are really cluttering up the hw/block directory. As suggested by Philippe previously, move the nvme emulation to hw/nvme. Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Keith Busch <kbusch@kernel.org>
This commit is contained in:
Klaus Jensen
parent
49ad39c55a
commit
88eea45c53
16 changed files with 217 additions and 216 deletions
509
hw/nvme/dif.c
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509
hw/nvme/dif.c
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@ -0,0 +1,509 @@
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/*
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* QEMU NVM Express End-to-End Data Protection support
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*
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* Copyright (c) 2021 Samsung Electronics Co., Ltd.
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*
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* Authors:
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* Klaus Jensen <k.jensen@samsung.com>
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* Gollu Appalanaidu <anaidu.gollu@samsung.com>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "sysemu/block-backend.h"
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#include "nvme.h"
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#include "trace.h"
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uint16_t nvme_check_prinfo(NvmeNamespace *ns, uint16_t ctrl, uint64_t slba,
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uint32_t reftag)
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{
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if ((NVME_ID_NS_DPS_TYPE(ns->id_ns.dps) == NVME_ID_NS_DPS_TYPE_1) &&
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(ctrl & NVME_RW_PRINFO_PRCHK_REF) && (slba & 0xffffffff) != reftag) {
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return NVME_INVALID_PROT_INFO | NVME_DNR;
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}
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return NVME_SUCCESS;
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}
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/* from Linux kernel (crypto/crct10dif_common.c) */
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static uint16_t crc_t10dif(uint16_t crc, const unsigned char *buffer,
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size_t len)
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{
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unsigned int i;
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for (i = 0; i < len; i++) {
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crc = (crc << 8) ^ t10_dif_crc_table[((crc >> 8) ^ buffer[i]) & 0xff];
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}
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return crc;
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}
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void nvme_dif_pract_generate_dif(NvmeNamespace *ns, uint8_t *buf, size_t len,
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uint8_t *mbuf, size_t mlen, uint16_t apptag,
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uint32_t reftag)
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{
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uint8_t *end = buf + len;
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int16_t pil = 0;
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if (!(ns->id_ns.dps & NVME_ID_NS_DPS_FIRST_EIGHT)) {
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pil = ns->lbaf.ms - sizeof(NvmeDifTuple);
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}
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trace_pci_nvme_dif_pract_generate_dif(len, ns->lbasz, ns->lbasz + pil,
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apptag, reftag);
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for (; buf < end; buf += ns->lbasz, mbuf += ns->lbaf.ms) {
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NvmeDifTuple *dif = (NvmeDifTuple *)(mbuf + pil);
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uint16_t crc = crc_t10dif(0x0, buf, ns->lbasz);
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if (pil) {
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crc = crc_t10dif(crc, mbuf, pil);
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}
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dif->guard = cpu_to_be16(crc);
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dif->apptag = cpu_to_be16(apptag);
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dif->reftag = cpu_to_be32(reftag);
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if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps) != NVME_ID_NS_DPS_TYPE_3) {
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reftag++;
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}
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}
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}
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static uint16_t nvme_dif_prchk(NvmeNamespace *ns, NvmeDifTuple *dif,
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uint8_t *buf, uint8_t *mbuf, size_t pil,
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uint16_t ctrl, uint16_t apptag,
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uint16_t appmask, uint32_t reftag)
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{
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switch (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
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case NVME_ID_NS_DPS_TYPE_3:
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if (be32_to_cpu(dif->reftag) != 0xffffffff) {
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break;
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}
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/* fallthrough */
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case NVME_ID_NS_DPS_TYPE_1:
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case NVME_ID_NS_DPS_TYPE_2:
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if (be16_to_cpu(dif->apptag) != 0xffff) {
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break;
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}
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trace_pci_nvme_dif_prchk_disabled(be16_to_cpu(dif->apptag),
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be32_to_cpu(dif->reftag));
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return NVME_SUCCESS;
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}
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if (ctrl & NVME_RW_PRINFO_PRCHK_GUARD) {
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uint16_t crc = crc_t10dif(0x0, buf, ns->lbasz);
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if (pil) {
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crc = crc_t10dif(crc, mbuf, pil);
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}
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trace_pci_nvme_dif_prchk_guard(be16_to_cpu(dif->guard), crc);
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if (be16_to_cpu(dif->guard) != crc) {
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return NVME_E2E_GUARD_ERROR;
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}
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}
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if (ctrl & NVME_RW_PRINFO_PRCHK_APP) {
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trace_pci_nvme_dif_prchk_apptag(be16_to_cpu(dif->apptag), apptag,
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appmask);
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if ((be16_to_cpu(dif->apptag) & appmask) != (apptag & appmask)) {
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return NVME_E2E_APP_ERROR;
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}
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}
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if (ctrl & NVME_RW_PRINFO_PRCHK_REF) {
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trace_pci_nvme_dif_prchk_reftag(be32_to_cpu(dif->reftag), reftag);
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if (be32_to_cpu(dif->reftag) != reftag) {
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return NVME_E2E_REF_ERROR;
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}
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}
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return NVME_SUCCESS;
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}
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uint16_t nvme_dif_check(NvmeNamespace *ns, uint8_t *buf, size_t len,
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uint8_t *mbuf, size_t mlen, uint16_t ctrl,
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uint64_t slba, uint16_t apptag,
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uint16_t appmask, uint32_t reftag)
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{
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uint8_t *end = buf + len;
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int16_t pil = 0;
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uint16_t status;
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status = nvme_check_prinfo(ns, ctrl, slba, reftag);
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if (status) {
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return status;
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}
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if (!(ns->id_ns.dps & NVME_ID_NS_DPS_FIRST_EIGHT)) {
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pil = ns->lbaf.ms - sizeof(NvmeDifTuple);
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}
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trace_pci_nvme_dif_check(NVME_RW_PRINFO(ctrl), ns->lbasz + pil);
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for (; buf < end; buf += ns->lbasz, mbuf += ns->lbaf.ms) {
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NvmeDifTuple *dif = (NvmeDifTuple *)(mbuf + pil);
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status = nvme_dif_prchk(ns, dif, buf, mbuf, pil, ctrl, apptag,
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appmask, reftag);
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if (status) {
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return status;
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}
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if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps) != NVME_ID_NS_DPS_TYPE_3) {
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reftag++;
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}
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}
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return NVME_SUCCESS;
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}
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uint16_t nvme_dif_mangle_mdata(NvmeNamespace *ns, uint8_t *mbuf, size_t mlen,
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uint64_t slba)
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{
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BlockBackend *blk = ns->blkconf.blk;
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BlockDriverState *bs = blk_bs(blk);
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int64_t moffset = 0, offset = nvme_l2b(ns, slba);
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uint8_t *mbufp, *end;
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bool zeroed;
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int16_t pil = 0;
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int64_t bytes = (mlen / ns->lbaf.ms) << ns->lbaf.ds;
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int64_t pnum = 0;
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Error *err = NULL;
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if (!(ns->id_ns.dps & NVME_ID_NS_DPS_FIRST_EIGHT)) {
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pil = ns->lbaf.ms - sizeof(NvmeDifTuple);
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}
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do {
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int ret;
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bytes -= pnum;
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ret = bdrv_block_status(bs, offset, bytes, &pnum, NULL, NULL);
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if (ret < 0) {
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error_setg_errno(&err, -ret, "unable to get block status");
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error_report_err(err);
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return NVME_INTERNAL_DEV_ERROR;
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}
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zeroed = !!(ret & BDRV_BLOCK_ZERO);
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trace_pci_nvme_block_status(offset, bytes, pnum, ret, zeroed);
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if (zeroed) {
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mbufp = mbuf + moffset;
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mlen = (pnum >> ns->lbaf.ds) * ns->lbaf.ms;
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end = mbufp + mlen;
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for (; mbufp < end; mbufp += ns->lbaf.ms) {
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memset(mbufp + pil, 0xff, sizeof(NvmeDifTuple));
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}
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}
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moffset += (pnum >> ns->lbaf.ds) * ns->lbaf.ms;
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offset += pnum;
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} while (pnum != bytes);
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return NVME_SUCCESS;
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}
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static void nvme_dif_rw_cb(void *opaque, int ret)
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{
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NvmeBounceContext *ctx = opaque;
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NvmeRequest *req = ctx->req;
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NvmeNamespace *ns = req->ns;
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BlockBackend *blk = ns->blkconf.blk;
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trace_pci_nvme_dif_rw_cb(nvme_cid(req), blk_name(blk));
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qemu_iovec_destroy(&ctx->data.iov);
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g_free(ctx->data.bounce);
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qemu_iovec_destroy(&ctx->mdata.iov);
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g_free(ctx->mdata.bounce);
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g_free(ctx);
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nvme_rw_complete_cb(req, ret);
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}
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static void nvme_dif_rw_check_cb(void *opaque, int ret)
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{
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NvmeBounceContext *ctx = opaque;
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NvmeRequest *req = ctx->req;
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NvmeNamespace *ns = req->ns;
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NvmeCtrl *n = nvme_ctrl(req);
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NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
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uint64_t slba = le64_to_cpu(rw->slba);
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uint16_t ctrl = le16_to_cpu(rw->control);
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uint16_t apptag = le16_to_cpu(rw->apptag);
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uint16_t appmask = le16_to_cpu(rw->appmask);
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uint32_t reftag = le32_to_cpu(rw->reftag);
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uint16_t status;
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trace_pci_nvme_dif_rw_check_cb(nvme_cid(req), NVME_RW_PRINFO(ctrl), apptag,
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appmask, reftag);
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if (ret) {
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goto out;
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}
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status = nvme_dif_mangle_mdata(ns, ctx->mdata.bounce, ctx->mdata.iov.size,
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slba);
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if (status) {
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req->status = status;
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goto out;
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}
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status = nvme_dif_check(ns, ctx->data.bounce, ctx->data.iov.size,
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ctx->mdata.bounce, ctx->mdata.iov.size, ctrl,
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slba, apptag, appmask, reftag);
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if (status) {
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req->status = status;
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goto out;
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}
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status = nvme_bounce_data(n, ctx->data.bounce, ctx->data.iov.size,
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NVME_TX_DIRECTION_FROM_DEVICE, req);
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if (status) {
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req->status = status;
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goto out;
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}
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if (ctrl & NVME_RW_PRINFO_PRACT && ns->lbaf.ms == 8) {
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goto out;
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}
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status = nvme_bounce_mdata(n, ctx->mdata.bounce, ctx->mdata.iov.size,
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NVME_TX_DIRECTION_FROM_DEVICE, req);
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if (status) {
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req->status = status;
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}
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out:
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nvme_dif_rw_cb(ctx, ret);
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}
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static void nvme_dif_rw_mdata_in_cb(void *opaque, int ret)
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{
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NvmeBounceContext *ctx = opaque;
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NvmeRequest *req = ctx->req;
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NvmeNamespace *ns = req->ns;
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NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
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uint64_t slba = le64_to_cpu(rw->slba);
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uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
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size_t mlen = nvme_m2b(ns, nlb);
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uint64_t offset = nvme_moff(ns, slba);
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BlockBackend *blk = ns->blkconf.blk;
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trace_pci_nvme_dif_rw_mdata_in_cb(nvme_cid(req), blk_name(blk));
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if (ret) {
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goto out;
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}
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ctx->mdata.bounce = g_malloc(mlen);
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qemu_iovec_reset(&ctx->mdata.iov);
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qemu_iovec_add(&ctx->mdata.iov, ctx->mdata.bounce, mlen);
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req->aiocb = blk_aio_preadv(blk, offset, &ctx->mdata.iov, 0,
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nvme_dif_rw_check_cb, ctx);
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return;
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out:
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nvme_dif_rw_cb(ctx, ret);
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}
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static void nvme_dif_rw_mdata_out_cb(void *opaque, int ret)
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{
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NvmeBounceContext *ctx = opaque;
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NvmeRequest *req = ctx->req;
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NvmeNamespace *ns = req->ns;
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NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
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uint64_t slba = le64_to_cpu(rw->slba);
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uint64_t offset = nvme_moff(ns, slba);
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BlockBackend *blk = ns->blkconf.blk;
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trace_pci_nvme_dif_rw_mdata_out_cb(nvme_cid(req), blk_name(blk));
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if (ret) {
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goto out;
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}
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req->aiocb = blk_aio_pwritev(blk, offset, &ctx->mdata.iov, 0,
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nvme_dif_rw_cb, ctx);
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return;
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out:
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nvme_dif_rw_cb(ctx, ret);
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}
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uint16_t nvme_dif_rw(NvmeCtrl *n, NvmeRequest *req)
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{
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NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
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NvmeNamespace *ns = req->ns;
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BlockBackend *blk = ns->blkconf.blk;
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bool wrz = rw->opcode == NVME_CMD_WRITE_ZEROES;
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uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
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uint64_t slba = le64_to_cpu(rw->slba);
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size_t len = nvme_l2b(ns, nlb);
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size_t mlen = nvme_m2b(ns, nlb);
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size_t mapped_len = len;
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int64_t offset = nvme_l2b(ns, slba);
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uint16_t ctrl = le16_to_cpu(rw->control);
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uint16_t apptag = le16_to_cpu(rw->apptag);
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uint16_t appmask = le16_to_cpu(rw->appmask);
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uint32_t reftag = le32_to_cpu(rw->reftag);
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bool pract = !!(ctrl & NVME_RW_PRINFO_PRACT);
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NvmeBounceContext *ctx;
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uint16_t status;
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trace_pci_nvme_dif_rw(pract, NVME_RW_PRINFO(ctrl));
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ctx = g_new0(NvmeBounceContext, 1);
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ctx->req = req;
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if (wrz) {
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BdrvRequestFlags flags = BDRV_REQ_MAY_UNMAP;
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if (ctrl & NVME_RW_PRINFO_PRCHK_MASK) {
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status = NVME_INVALID_PROT_INFO | NVME_DNR;
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goto err;
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}
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if (pract) {
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uint8_t *mbuf, *end;
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int16_t pil = ns->lbaf.ms - sizeof(NvmeDifTuple);
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status = nvme_check_prinfo(ns, ctrl, slba, reftag);
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if (status) {
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goto err;
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}
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|
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flags = 0;
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ctx->mdata.bounce = g_malloc0(mlen);
|
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|
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qemu_iovec_init(&ctx->mdata.iov, 1);
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qemu_iovec_add(&ctx->mdata.iov, ctx->mdata.bounce, mlen);
|
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mbuf = ctx->mdata.bounce;
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end = mbuf + mlen;
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|
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if (ns->id_ns.dps & NVME_ID_NS_DPS_FIRST_EIGHT) {
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pil = 0;
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}
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for (; mbuf < end; mbuf += ns->lbaf.ms) {
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NvmeDifTuple *dif = (NvmeDifTuple *)(mbuf + pil);
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dif->apptag = cpu_to_be16(apptag);
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dif->reftag = cpu_to_be32(reftag);
|
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|
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switch (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
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case NVME_ID_NS_DPS_TYPE_1:
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case NVME_ID_NS_DPS_TYPE_2:
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reftag++;
|
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}
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}
|
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}
|
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|
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req->aiocb = blk_aio_pwrite_zeroes(blk, offset, len, flags,
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nvme_dif_rw_mdata_out_cb, ctx);
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return NVME_NO_COMPLETE;
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}
|
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|
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if (nvme_ns_ext(ns) && !(pract && ns->lbaf.ms == 8)) {
|
||||
mapped_len += mlen;
|
||||
}
|
||||
|
||||
status = nvme_map_dptr(n, &req->sg, mapped_len, &req->cmd);
|
||||
if (status) {
|
||||
goto err;
|
||||
}
|
||||
|
||||
ctx->data.bounce = g_malloc(len);
|
||||
|
||||
qemu_iovec_init(&ctx->data.iov, 1);
|
||||
qemu_iovec_add(&ctx->data.iov, ctx->data.bounce, len);
|
||||
|
||||
if (req->cmd.opcode == NVME_CMD_READ) {
|
||||
block_acct_start(blk_get_stats(blk), &req->acct, ctx->data.iov.size,
|
||||
BLOCK_ACCT_READ);
|
||||
|
||||
req->aiocb = blk_aio_preadv(ns->blkconf.blk, offset, &ctx->data.iov, 0,
|
||||
nvme_dif_rw_mdata_in_cb, ctx);
|
||||
return NVME_NO_COMPLETE;
|
||||
}
|
||||
|
||||
status = nvme_bounce_data(n, ctx->data.bounce, ctx->data.iov.size,
|
||||
NVME_TX_DIRECTION_TO_DEVICE, req);
|
||||
if (status) {
|
||||
goto err;
|
||||
}
|
||||
|
||||
ctx->mdata.bounce = g_malloc(mlen);
|
||||
|
||||
qemu_iovec_init(&ctx->mdata.iov, 1);
|
||||
qemu_iovec_add(&ctx->mdata.iov, ctx->mdata.bounce, mlen);
|
||||
|
||||
if (!(pract && ns->lbaf.ms == 8)) {
|
||||
status = nvme_bounce_mdata(n, ctx->mdata.bounce, ctx->mdata.iov.size,
|
||||
NVME_TX_DIRECTION_TO_DEVICE, req);
|
||||
if (status) {
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
status = nvme_check_prinfo(ns, ctrl, slba, reftag);
|
||||
if (status) {
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (pract) {
|
||||
/* splice generated protection information into the buffer */
|
||||
nvme_dif_pract_generate_dif(ns, ctx->data.bounce, ctx->data.iov.size,
|
||||
ctx->mdata.bounce, ctx->mdata.iov.size,
|
||||
apptag, reftag);
|
||||
} else {
|
||||
status = nvme_dif_check(ns, ctx->data.bounce, ctx->data.iov.size,
|
||||
ctx->mdata.bounce, ctx->mdata.iov.size, ctrl,
|
||||
slba, apptag, appmask, reftag);
|
||||
if (status) {
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
block_acct_start(blk_get_stats(blk), &req->acct, ctx->data.iov.size,
|
||||
BLOCK_ACCT_WRITE);
|
||||
|
||||
req->aiocb = blk_aio_pwritev(ns->blkconf.blk, offset, &ctx->data.iov, 0,
|
||||
nvme_dif_rw_mdata_out_cb, ctx);
|
||||
|
||||
return NVME_NO_COMPLETE;
|
||||
|
||||
err:
|
||||
qemu_iovec_destroy(&ctx->data.iov);
|
||||
g_free(ctx->data.bounce);
|
||||
|
||||
qemu_iovec_destroy(&ctx->mdata.iov);
|
||||
g_free(ctx->mdata.bounce);
|
||||
|
||||
g_free(ctx);
|
||||
|
||||
return status;
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue