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test/qtest/hace: Support to test upper 32 bits of digest and source addresses

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Added "src_hi" and "dest_hi" fields to "AspeedMasks" for 64-bit addresses test.
Updated "aspeed_test_addresses" to validate "HACE_HASH_SRC_HI" and
"HACE_HASH_DIGEST_HI".
Ensured correct masking of 64-bit addresses by checking both lower and upper
32-bit registers.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Fabiano Rosas <farosas@suse.de>
Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-27-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-05-15 16:09:58 +08:00 • committed by Cédric Le Goater
parent 5ced818e42
commit 88d8515fb7
2 changed files with 16 additions and 1 deletions
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15
tests/qtest/aspeed-hace-utils.c
View file

@ -588,30 +588,43 @@ void aspeed_test_addresses(const char *machine, const uint32_t base,
*/
g_assert_cmphex(qtest_readl(s, base + HACE_CMD), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0);
/* Check that the address masking is correct */
qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, expected->src);
qtest_writel(s, base + HACE_HASH_SRC_HI, 0xffffffff);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI),
==, expected->src_hi);
qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==,
expected->dest);
qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0xffffffff);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==,
expected->dest_hi);
qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==,
expected->len);
/* Reset to zero */
qtest_writel(s, base + HACE_HASH_SRC, 0);
qtest_writel(s, base + HACE_HASH_SRC_HI, 0);
qtest_writel(s, base + HACE_HASH_DIGEST, 0);
qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0);
qtest_writel(s, base + HACE_HASH_DATA_LEN, 0);
/* Check that all bits are now zero */
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0);
qtest_quit(s);

2
tests/qtest/aspeed-hace-utils.h
View file

@ -51,6 +51,8 @@ struct AspeedMasks {
uint32_t src;
uint32_t dest;
uint32_t len;
uint32_t src_hi;
uint32_t dest_hi;
};
void aspeed_test_md5(const char *machine, const uint32_t base,