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target-arm queue:

Browse source 
* docs/devel/docs: Document .hx file syntax
  * arm_pamax() no longer needs to do feature propagation
  * docs/system/arm/virt.rst: Improve 'highmem' option docs
  * STM32L4x5 Implement SYSCFG and EXTI devices
  * hw/timer: fix systick trace message
  * hw/arm/virt: Consolidate valid CPU types
  * load_elf: fix iterator's type for elf file processing
 -----BEGIN PGP SIGNATURE-----
 
 iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmWpHM4ZHHBldGVyLm1h
 eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pZxD/sGIXvTeoOCsum7OFpArKoQ
 J+wcy74pO526IDzjudgtwP8kFW09oVblMPgrt/68F9LY4Oa7sDNAZX/Xqlhs/hdJ
 SVbOXArRmyLvgLpn8KVii9xk9iI/olMGt0S6KcXAErdgFud+JcCevbS0D5fAF4Ua
 /G/4ldnwr+WcYUA5IIoi02ymSBm5VNeH2bKu0MPS3xpizjzgOFxWTBYwq3zkZYWD
 w5GjH9+F+IC67CiAlCLvuQBqpGLdRwFBttU05hLtGXuSlnvS+FtJTooI7gGD17CR
 2wTa7qF716qDN1lNSIvxA6t8/dWNMIYCZYdlxJml476WzP3jECpth2WFWqE0G3yg
 Orr7sFVB8X6JmtlR34srW6e3CZA3t+4FIWqcdELFLi5IQtJeer90jqQ9xwx4SttJ
 nsHdy5M8txWSa61yAaDTXMID/smVlC7sWTKJrR9kV7v5+b9OPQ/R8k0mCODl5Aer
 mzAVuCvUQVYK3j7fzprGrlldla57s3v78OAhqACLgKflK0+aJSJjglulPrSMK1z5
 bRPS5jLZjFwEi2VaLVg3LPJiBMDj1s/wAl0ycfCQSv2oEzvmpkw+Ar1HDc2NFe+d
 9dunbdhAZJMwh+ABIg7iMj+l0ncOXDa4DS+6BnjRxfECCa172u3viq1HATkLLAFI
 GTkcJ5hIQzNEeg9ob0MDIg==
 =Rfpe
 -----END PGP SIGNATURE-----

Merge tag 'pull-target-arm-20240118' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * docs/devel/docs: Document .hx file syntax
 * arm_pamax() no longer needs to do feature propagation
 * docs/system/arm/virt.rst: Improve 'highmem' option docs
 * STM32L4x5 Implement SYSCFG and EXTI devices
 * hw/timer: fix systick trace message
 * hw/arm/virt: Consolidate valid CPU types
 * load_elf: fix iterator's type for elf file processing

# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmWpHM4ZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pZxD/sGIXvTeoOCsum7OFpArKoQ
# J+wcy74pO526IDzjudgtwP8kFW09oVblMPgrt/68F9LY4Oa7sDNAZX/Xqlhs/hdJ
# SVbOXArRmyLvgLpn8KVii9xk9iI/olMGt0S6KcXAErdgFud+JcCevbS0D5fAF4Ua
# /G/4ldnwr+WcYUA5IIoi02ymSBm5VNeH2bKu0MPS3xpizjzgOFxWTBYwq3zkZYWD
# w5GjH9+F+IC67CiAlCLvuQBqpGLdRwFBttU05hLtGXuSlnvS+FtJTooI7gGD17CR
# 2wTa7qF716qDN1lNSIvxA6t8/dWNMIYCZYdlxJml476WzP3jECpth2WFWqE0G3yg
# Orr7sFVB8X6JmtlR34srW6e3CZA3t+4FIWqcdELFLi5IQtJeer90jqQ9xwx4SttJ
# nsHdy5M8txWSa61yAaDTXMID/smVlC7sWTKJrR9kV7v5+b9OPQ/R8k0mCODl5Aer
# mzAVuCvUQVYK3j7fzprGrlldla57s3v78OAhqACLgKflK0+aJSJjglulPrSMK1z5
# bRPS5jLZjFwEi2VaLVg3LPJiBMDj1s/wAl0ycfCQSv2oEzvmpkw+Ar1HDc2NFe+d
# 9dunbdhAZJMwh+ABIg7iMj+l0ncOXDa4DS+6BnjRxfECCa172u3viq1HATkLLAFI
# GTkcJ5hIQzNEeg9ob0MDIg==
# =Rfpe
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 18 Jan 2024 12:42:54 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20240118' of https://git.linaro.org/people/pmaydell/qemu-arm:
  load_elf: fix iterator's type for elf file processing
  hw/arm/virt: Consolidate valid CPU types
  hw/timer: fix systick trace message
  tests/qtest: Add STM32L4x5 SYSCFG QTest testcase
  hw/arm: Connect STM32L4x5 SYSCFG to STM32L4x5 SoC
  hw/misc: Implement STM32L4x5 SYSCFG
  tests/qtest: Add STM32L4x5 EXTI QTest testcase
  hw/arm: Connect STM32L4x5 EXTI to STM32L4x5 SoC
  hw/misc: Implement STM32L4x5 EXTI
  docs/system/arm/virt.rst: Improve 'highmem' option docs
  target/arm: arm_pamax() no longer needs to do feature propagation
  docs/devel/docs: Document .hx file syntax

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-01-18 12:48:17 +00:00
commit 88cf5fec91
26 changed files with 1719 additions and 29 deletions
Download patch file Download diff file Expand all files Collapse all files

6
tests/qtest/meson.build
View file

@ -196,6 +196,11 @@ qtests_aspeed = \
['aspeed_hace-test',
'aspeed_smc-test',
'aspeed_gpio-test']
qtests_stm32l4x5 = \
['stm32l4x5_exti-test',
'stm32l4x5_syscfg-test']
qtests_arm = \
(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
(config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \
@ -209,6 +214,7 @@ qtests_arm = \
(config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
(config_all_devices.has_key('CONFIG_VEXPRESS') ? ['test-arm-mptimer'] : []) + \
(config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
(config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 : []) + \
['arm-cpu-features',
'boot-serial-test']

524
tests/qtest/stm32l4x5_exti-test.c Normal file
View file

@ -0,0 +1,524 @@
/*
* QTest testcase for STM32L4x5_EXTI
*
* Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
* Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "libqtest-single.h"
#define EXTI_BASE_ADDR 0x40010400
#define EXTI_IMR1 0x00
#define EXTI_EMR1 0x04
#define EXTI_RTSR1 0x08
#define EXTI_FTSR1 0x0C
#define EXTI_SWIER1 0x10
#define EXTI_PR1 0x14
#define EXTI_IMR2 0x20
#define EXTI_EMR2 0x24
#define EXTI_RTSR2 0x28
#define EXTI_FTSR2 0x2C
#define EXTI_SWIER2 0x30
#define EXTI_PR2 0x34
#define NVIC_ISER 0xE000E100
#define NVIC_ISPR 0xE000E200
#define NVIC_ICPR 0xE000E280
#define EXTI0_IRQ 6
#define EXTI1_IRQ 7
#define EXTI35_IRQ 1
static void enable_nvic_irq(unsigned int n)
{
writel(NVIC_ISER, 1 << n);
}
static void unpend_nvic_irq(unsigned int n)
{
writel(NVIC_ICPR, 1 << n);
}
static bool check_nvic_pending(unsigned int n)
{
return readl(NVIC_ISPR) & (1 << n);
}
static void exti_writel(unsigned int offset, uint32_t value)
{
writel(EXTI_BASE_ADDR + offset, value);
}
static uint32_t exti_readl(unsigned int offset)
{
return readl(EXTI_BASE_ADDR + offset);
}
static void exti_set_irq(int num, int level)
{
qtest_set_irq_in(global_qtest, "/machine/soc/exti", NULL,
num, level);
}
static void test_reg_write_read(void)
{
/* Test that non-reserved bits in xMR and xTSR can be set and cleared */
exti_writel(EXTI_IMR1, 0xFFFFFFFF);
g_assert_cmpuint(exti_readl(EXTI_IMR1), ==, 0xFFFFFFFF);
exti_writel(EXTI_IMR1, 0x00000000);
g_assert_cmpuint(exti_readl(EXTI_IMR1), ==, 0x00000000);
exti_writel(EXTI_EMR1, 0xFFFFFFFF);
g_assert_cmpuint(exti_readl(EXTI_EMR1), ==, 0xFFFFFFFF);
exti_writel(EXTI_EMR1, 0x00000000);
g_assert_cmpuint(exti_readl(EXTI_EMR1), ==, 0x00000000);
exti_writel(EXTI_RTSR1, 0xFFFFFFFF);
g_assert_cmpuint(exti_readl(EXTI_RTSR1), ==, 0x007DFFFF);
exti_writel(EXTI_RTSR1, 0x00000000);
g_assert_cmpuint(exti_readl(EXTI_RTSR1), ==, 0x00000000);
exti_writel(EXTI_FTSR1, 0xFFFFFFFF);
g_assert_cmpuint(exti_readl(EXTI_FTSR1), ==, 0x007DFFFF);
exti_writel(EXTI_FTSR1, 0x00000000);
g_assert_cmpuint(exti_readl(EXTI_FTSR1), ==, 0x00000000);
exti_writel(EXTI_IMR2, 0xFFFFFFFF);
g_assert_cmpuint(exti_readl(EXTI_IMR2), ==, 0x000000FF);
exti_writel(EXTI_IMR2, 0x00000000);
g_assert_cmpuint(exti_readl(EXTI_IMR2), ==, 0x00000000);
exti_writel(EXTI_EMR2, 0xFFFFFFFF);
g_assert_cmpuint(exti_readl(EXTI_EMR2), ==, 0x000000FF);
exti_writel(EXTI_EMR2, 0x00000000);
g_assert_cmpuint(exti_readl(EXTI_EMR2), ==, 0x00000000);
exti_writel(EXTI_RTSR2, 0xFFFFFFFF);
g_assert_cmpuint(exti_readl(EXTI_RTSR2), ==, 0x00000078);
exti_writel(EXTI_RTSR2, 0x00000000);
g_assert_cmpuint(exti_readl(EXTI_RTSR2), ==, 0x00000000);
exti_writel(EXTI_FTSR2, 0xFFFFFFFF);
g_assert_cmpuint(exti_readl(EXTI_FTSR2), ==, 0x00000078);
exti_writel(EXTI_FTSR2, 0x00000000);
g_assert_cmpuint(exti_readl(EXTI_FTSR2), ==, 0x00000000);
}
static void test_direct_lines_write(void)
{
/* Test that direct lines reserved bits are not written to */
exti_writel(EXTI_RTSR1, 0xFF820000);
g_assert_cmpuint(exti_readl(EXTI_RTSR1), ==, 0x00000000);
exti_writel(EXTI_FTSR1, 0xFF820000);
g_assert_cmpuint(exti_readl(EXTI_FTSR1), ==, 0x00000000);
exti_writel(EXTI_SWIER1, 0xFF820000);
g_assert_cmpuint(exti_readl(EXTI_SWIER1), ==, 0x00000000);
exti_writel(EXTI_PR1, 0xFF820000);
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
exti_writel(EXTI_RTSR2, 0x00000087);
g_assert_cmpuint(exti_readl(EXTI_RTSR2), ==, 0x00000000);
exti_writel(EXTI_FTSR2, 0x00000087);
g_assert_cmpuint(exti_readl(EXTI_FTSR2), ==, 0x00000000);
exti_writel(EXTI_SWIER2, 0x00000087);
g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000000);
exti_writel(EXTI_PR2, 0x00000087);
g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
}
static void test_reserved_bits_write(void)
{
/* Test that reserved bits stay are not written to */
exti_writel(EXTI_IMR2, 0xFFFFFF00);
g_assert_cmpuint(exti_readl(EXTI_IMR2), ==, 0x00000000);
exti_writel(EXTI_EMR2, 0xFFFFFF00);
g_assert_cmpuint(exti_readl(EXTI_EMR2), ==, 0x00000000);
exti_writel(EXTI_RTSR2, 0xFFFFFF00);
g_assert_cmpuint(exti_readl(EXTI_RTSR2), ==, 0x00000000);
exti_writel(EXTI_FTSR2, 0xFFFFFF00);
g_assert_cmpuint(exti_readl(EXTI_FTSR2), ==, 0x00000000);
exti_writel(EXTI_SWIER2, 0xFFFFFF00);
g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000000);
exti_writel(EXTI_PR2, 0xFFFFFF00);
g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
}
static void test_software_interrupt(void)
{
/*
* Test that we can launch a software irq by :
* - enabling its line in IMR
* - and then setting a bit from '0' to '1' in SWIER
*
* And that the interruption stays pending in NVIC
* even after clearing the pending bit in PR.
*/
/*
* Testing interrupt line EXTI0
* Bit 0 in EXTI_*1 registers (EXTI0) corresponds to GPIO Px_0
*/
enable_nvic_irq(EXTI0_IRQ);
/* Check that there are no interrupts already pending in PR */
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
/* Check that this specific interrupt isn't pending in NVIC */
g_assert_false(check_nvic_pending(EXTI0_IRQ));
/* Enable interrupt line EXTI0 */
exti_writel(EXTI_IMR1, 0x00000001);
/* Set the right SWIER bit from '0' to '1' */
exti_writel(EXTI_SWIER1, 0x00000000);
exti_writel(EXTI_SWIER1, 0x00000001);
/* Check that the write in SWIER was effective */
g_assert_cmpuint(exti_readl(EXTI_SWIER1), ==, 0x00000001);
/* Check that the corresponding pending bit in PR is set */
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
/* Check that the corresponding interrupt is pending in the NVIC */
g_assert_true(check_nvic_pending(EXTI0_IRQ));
/* Clear the pending bit in PR */
exti_writel(EXTI_PR1, 0x00000001);
/* Check that the write in PR was effective */
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
/* Check that the corresponding bit in SWIER was cleared */
g_assert_cmpuint(exti_readl(EXTI_SWIER1), ==, 0x00000000);
/* Check that the interrupt is still pending in the NVIC */
g_assert_true(check_nvic_pending(EXTI0_IRQ));
/*
* Testing interrupt line EXTI35
* Bit 3 in EXTI_*2 registers (EXTI35) corresponds to PVM 1 Wakeup
*/
enable_nvic_irq(EXTI35_IRQ);
/* Check that there are no interrupts already pending */
g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
g_assert_false(check_nvic_pending(EXTI35_IRQ));
/* Enable interrupt line EXTI0 */
exti_writel(EXTI_IMR2, 0x00000008);
/* Set the right SWIER bit from '0' to '1' */
exti_writel(EXTI_SWIER2, 0x00000000);
exti_writel(EXTI_SWIER2, 0x00000008);
/* Check that the write in SWIER was effective */
g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000008);
/* Check that the corresponding pending bit in PR is set */
g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000008);
/* Check that the corresponding interrupt is pending in the NVIC */
g_assert_true(check_nvic_pending(EXTI35_IRQ));
/* Clear the pending bit in PR */
exti_writel(EXTI_PR2, 0x00000008);
/* Check that the write in PR was effective */
g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
/* Check that the corresponding bit in SWIER was cleared */
g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000000);
/* Check that the interrupt is still pending in the NVIC */
g_assert_true(check_nvic_pending(EXTI35_IRQ));
/* Clean NVIC */
unpend_nvic_irq(EXTI0_IRQ);
g_assert_false(check_nvic_pending(EXTI0_IRQ));
unpend_nvic_irq(EXTI35_IRQ);
g_assert_false(check_nvic_pending(EXTI35_IRQ));
}
static void test_edge_selector(void)
{
enable_nvic_irq(EXTI0_IRQ);
/* Configure EXTI line 0 irq on rising edge */
exti_set_irq(0, 1);
exti_writel(EXTI_IMR1, 0x00000001);
exti_writel(EXTI_RTSR1, 0x00000001);
exti_writel(EXTI_FTSR1, 0x00000000);
/* Test that an irq is raised on rising edge only */
exti_set_irq(0, 0);
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
g_assert_false(check_nvic_pending(EXTI0_IRQ));
exti_set_irq(0, 1);
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
g_assert_true(check_nvic_pending(EXTI0_IRQ));
/* Clean the test */
exti_writel(EXTI_PR1, 0x00000001);
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
unpend_nvic_irq(EXTI0_IRQ);
g_assert_false(check_nvic_pending(EXTI0_IRQ));
/* Configure EXTI line 0 irq on falling edge */
exti_set_irq(0, 0);
exti_writel(EXTI_IMR1, 0x00000001);
exti_writel(EXTI_RTSR1, 0x00000000);
exti_writel(EXTI_FTSR1, 0x00000001);
/* Test that an irq is raised on falling edge only */
exti_set_irq(0, 1);
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
g_assert_false(check_nvic_pending(EXTI0_IRQ));
exti_set_irq(0, 0);
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
g_assert_true(check_nvic_pending(EXTI0_IRQ));
/* Clean the test */
exti_writel(EXTI_PR1, 0x00000001);
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
unpend_nvic_irq(EXTI0_IRQ);
g_assert_false(check_nvic_pending(EXTI0_IRQ));
/* Configure EXTI line 0 irq on falling and rising edge */
exti_writel(EXTI_IMR1, 0x00000001);
exti_writel(EXTI_RTSR1, 0x00000001);
exti_writel(EXTI_FTSR1, 0x00000001);
/* Test that an irq is raised on rising edge */
exti_set_irq(0, 1);
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
g_assert_true(check_nvic_pending(EXTI0_IRQ));
/* Clean the test */
exti_writel(EXTI_PR1, 0x00000001);
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
unpend_nvic_irq(EXTI0_IRQ);
g_assert_false(check_nvic_pending(EXTI0_IRQ));
/* Test that an irq is raised on falling edge */
exti_set_irq(0, 0);
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
g_assert_true(check_nvic_pending(EXTI0_IRQ));
/* Clean the test */
exti_writel(EXTI_PR1, 0x00000001);
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
unpend_nvic_irq(EXTI0_IRQ);
g_assert_false(check_nvic_pending(EXTI0_IRQ));
/* Configure EXTI line 0 irq without selecting an edge trigger */
exti_writel(EXTI_IMR1, 0x00000001);
exti_writel(EXTI_RTSR1, 0x00000000);
exti_writel(EXTI_FTSR1, 0x00000000);
/* Test that no irq is raised */
exti_set_irq(0, 1);
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
g_assert_false(check_nvic_pending(EXTI0_IRQ));
exti_set_irq(0, 0);
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
g_assert_false(check_nvic_pending(EXTI0_IRQ));
}
static void test_no_software_interrupt(void)
{
/*
* Test that software irq doesn't happen when :
* - corresponding bit in IMR isn't set
* - SWIER is set to 1 before IMR is set to 1
*/
/*
* Testing interrupt line EXTI0
* Bit 0 in EXTI_*1 registers (EXTI0) corresponds to GPIO Px_0
*/
enable_nvic_irq(EXTI0_IRQ);
/* Check that there are no interrupts already pending in PR */
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
/* Check that this specific interrupt isn't pending in NVIC */
g_assert_false(check_nvic_pending(EXTI0_IRQ));
/* Mask interrupt line EXTI0 */
exti_writel(EXTI_IMR1, 0x00000000);
/* Set the corresponding SWIER bit from '0' to '1' */
exti_writel(EXTI_SWIER1, 0x00000000);
exti_writel(EXTI_SWIER1, 0x00000001);
/* Check that the write in SWIER was effective */
g_assert_cmpuint(exti_readl(EXTI_SWIER1), ==, 0x00000001);
/* Check that the pending bit in PR wasn't set */
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
/* Check that the interrupt isn't pending in NVIC */
g_assert_false(check_nvic_pending(EXTI0_IRQ));
/* Enable interrupt line EXTI0 */
exti_writel(EXTI_IMR1, 0x00000001);
/* Check that the pending bit in PR wasn't set */
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
/* Check that the interrupt isn't pending in NVIC */
g_assert_false(check_nvic_pending(EXTI0_IRQ));
/*
* Testing interrupt line EXTI35
* Bit 3 in EXTI_*2 registers (EXTI35) corresponds to PVM 1 Wakeup
*/
enable_nvic_irq(EXTI35_IRQ);
/* Check that there are no interrupts already pending in PR */
g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
/* Check that this specific interrupt isn't pending in NVIC */
g_assert_false(check_nvic_pending(EXTI35_IRQ));
/* Mask interrupt line EXTI35 */
exti_writel(EXTI_IMR2, 0x00000000);
/* Set the corresponding SWIER bit from '0' to '1' */
exti_writel(EXTI_SWIER2, 0x00000000);
exti_writel(EXTI_SWIER2, 0x00000008);
/* Check that the write in SWIER was effective */
g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000008);
/* Check that the pending bit in PR wasn't set */
g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
/* Check that the interrupt isn't pending in NVIC */
g_assert_false(check_nvic_pending(EXTI35_IRQ));
/* Enable interrupt line EXTI35 */
exti_writel(EXTI_IMR2, 0x00000008);
/* Check that the pending bit in PR wasn't set */
g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
/* Check that the interrupt isn't pending in NVIC */
g_assert_false(check_nvic_pending(EXTI35_IRQ));
}
static void test_masked_interrupt(void)
{
/*
* Test that irq doesn't happen when :
* - corresponding bit in IMR isn't set
* - SWIER is set to 1 before IMR is set to 1
*/
/*
* Testing interrupt line EXTI1
* with rising edge from GPIOx pin 1
*/
enable_nvic_irq(EXTI1_IRQ);
/* Check that there are no interrupts already pending in PR */
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
/* Check that this specific interrupt isn't pending in NVIC */
g_assert_false(check_nvic_pending(EXTI1_IRQ));
/* Mask interrupt line EXTI1 */
exti_writel(EXTI_IMR1, 0x00000000);
/* Configure interrupt on rising edge */
exti_writel(EXTI_RTSR1, 0x00000002);
/* Simulate rising edge from GPIO line 1 */
exti_set_irq(1, 1);
/* Check that the pending bit in PR wasn't set */
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
/* Check that the interrupt isn't pending in NVIC */
g_assert_false(check_nvic_pending(EXTI1_IRQ));
/* Enable interrupt line EXTI1 */
exti_writel(EXTI_IMR1, 0x00000002);
/* Check that the pending bit in PR wasn't set */
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
/* Check that the interrupt isn't pending in NVIC */
g_assert_false(check_nvic_pending(EXTI1_IRQ));
}
static void test_interrupt(void)
{
/*
* Test that we can launch an irq by :
* - enabling its line in IMR
* - configuring interrupt on rising edge
* - and then setting the input line from '0' to '1'
*
* And that the interruption stays pending in NVIC
* even after clearing the pending bit in PR.
*/
/*
* Testing interrupt line EXTI1
* with rising edge from GPIOx pin 1
*/
enable_nvic_irq(EXTI1_IRQ);
/* Check that there are no interrupts already pending in PR */
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
/* Check that this specific interrupt isn't pending in NVIC */
g_assert_false(check_nvic_pending(EXTI1_IRQ));
/* Enable interrupt line EXTI1 */
exti_writel(EXTI_IMR1, 0x00000002);
/* Configure interrupt on rising edge */
exti_writel(EXTI_RTSR1, 0x00000002);
/* Simulate rising edge from GPIO line 1 */
exti_set_irq(1, 1);
/* Check that the pending bit in PR was set */
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000002);
/* Check that the interrupt is pending in NVIC */
g_assert_true(check_nvic_pending(EXTI1_IRQ));
/* Clear the pending bit in PR */
exti_writel(EXTI_PR1, 0x00000002);
/* Check that the write in PR was effective */
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
/* Check that the interrupt is still pending in the NVIC */
g_assert_true(check_nvic_pending(EXTI1_IRQ));
/* Clean NVIC */
unpend_nvic_irq(EXTI1_IRQ);
g_assert_false(check_nvic_pending(EXTI1_IRQ));
}
int main(int argc, char **argv)
{
int ret;
g_test_init(&argc, &argv, NULL);
g_test_set_nonfatal_assertions();
qtest_add_func("stm32l4x5/exti/direct_lines", test_direct_lines_write);
qtest_add_func("stm32l4x5/exti/reserved_bits", test_reserved_bits_write);
qtest_add_func("stm32l4x5/exti/reg_write_read", test_reg_write_read);
qtest_add_func("stm32l4x5/exti/no_software_interrupt",
test_no_software_interrupt);
qtest_add_func("stm32l4x5/exti/software_interrupt",
test_software_interrupt);
qtest_add_func("stm32l4x5/exti/masked_interrupt", test_masked_interrupt);
qtest_add_func("stm32l4x5/exti/interrupt", test_interrupt);
qtest_add_func("stm32l4x5/exti/test_edge_selector", test_edge_selector);
qtest_start("-machine b-l475e-iot01a");
ret = g_test_run();
qtest_end();
return ret;
}

331
tests/qtest/stm32l4x5_syscfg-test.c Normal file
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/*
* QTest testcase for STM32L4x5_SYSCFG
*
* Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
* Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "libqtest-single.h"
#define SYSCFG_BASE_ADDR 0x40010000
#define SYSCFG_MEMRMP 0x00
#define SYSCFG_CFGR1 0x04
#define SYSCFG_EXTICR1 0x08
#define SYSCFG_EXTICR2 0x0C
#define SYSCFG_EXTICR3 0x10
#define SYSCFG_EXTICR4 0x14
#define SYSCFG_SCSR 0x18
#define SYSCFG_CFGR2 0x1C
#define SYSCFG_SWPR 0x20
#define SYSCFG_SKR 0x24
#define SYSCFG_SWPR2 0x28
#define INVALID_ADDR 0x2C
static void syscfg_writel(unsigned int offset, uint32_t value)
{
writel(SYSCFG_BASE_ADDR + offset, value);
}
static uint32_t syscfg_readl(unsigned int offset)
{
return readl(SYSCFG_BASE_ADDR + offset);
}
static void syscfg_set_irq(int num, int level)
{
qtest_set_irq_in(global_qtest, "/machine/soc/syscfg",
NULL, num, level);
}
static void system_reset(void)
{
QDict *response;
response = qtest_qmp(global_qtest, "{'execute': 'system_reset'}");
g_assert(qdict_haskey(response, "return"));
qobject_unref(response);
}
static void test_reset(void)
{
/*
* Test that registers are initialized at the correct values
*/
g_assert_cmpuint(syscfg_readl(SYSCFG_MEMRMP), ==, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR1), ==, 0x7C000001);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR1), ==, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR2), ==, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR3), ==, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR4), ==, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_SCSR), ==, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR2), ==, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_SWPR), ==, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_SKR), ==, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_SWPR2), ==, 0x00000000);
}
static void test_reserved_bits(void)
{
/*
* Test that reserved bits stay at reset value
* (which is 0 for all of them) by writing '1'
* in all reserved bits (keeping reset value for
* other bits) and checking that the
* register is still at reset value
*/
syscfg_writel(SYSCFG_MEMRMP, 0xFFFFFEF8);
g_assert_cmpuint(syscfg_readl(SYSCFG_MEMRMP), ==, 0x00000000);
syscfg_writel(SYSCFG_CFGR1, 0x7F00FEFF);
g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR1), ==, 0x7C000001);
syscfg_writel(SYSCFG_EXTICR1, 0xFFFF0000);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR1), ==, 0x00000000);
syscfg_writel(SYSCFG_EXTICR2, 0xFFFF0000);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR2), ==, 0x00000000);
syscfg_writel(SYSCFG_EXTICR3, 0xFFFF0000);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR3), ==, 0x00000000);
syscfg_writel(SYSCFG_EXTICR4, 0xFFFF0000);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR4), ==, 0x00000000);
syscfg_writel(SYSCFG_SKR, 0xFFFFFF00);
g_assert_cmpuint(syscfg_readl(SYSCFG_SKR), ==, 0x00000000);
}
static void test_set_and_clear(void)
{
/*
* Test that regular bits can be set and cleared
*/
syscfg_writel(SYSCFG_MEMRMP, 0x00000107);
g_assert_cmpuint(syscfg_readl(SYSCFG_MEMRMP), ==, 0x00000107);
syscfg_writel(SYSCFG_MEMRMP, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_MEMRMP), ==, 0x00000000);
/* cfgr1 bit 0 is clear only so we keep it set */
syscfg_writel(SYSCFG_CFGR1, 0xFCFF0101);
g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR1), ==, 0xFCFF0101);
syscfg_writel(SYSCFG_CFGR1, 0x00000001);
g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR1), ==, 0x00000001);
syscfg_writel(SYSCFG_EXTICR1, 0x0000FFFF);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR1), ==, 0x0000FFFF);
syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR1), ==, 0x00000000);
syscfg_writel(SYSCFG_EXTICR2, 0x0000FFFF);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR2), ==, 0x0000FFFF);
syscfg_writel(SYSCFG_EXTICR2, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR2), ==, 0x00000000);
syscfg_writel(SYSCFG_EXTICR3, 0x0000FFFF);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR3), ==, 0x0000FFFF);
syscfg_writel(SYSCFG_EXTICR3, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR3), ==, 0x00000000);
syscfg_writel(SYSCFG_EXTICR4, 0x0000FFFF);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR4), ==, 0x0000FFFF);
syscfg_writel(SYSCFG_EXTICR4, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR4), ==, 0x00000000);
syscfg_writel(SYSCFG_SKR, 0x000000FF);
g_assert_cmpuint(syscfg_readl(SYSCFG_SKR), ==, 0x000000FF);
syscfg_writel(SYSCFG_SKR, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_SKR), ==, 0x00000000);
}
static void test_clear_by_writing_1(void)
{
/*
* Test that writing '1' doesn't set the bit
*/
syscfg_writel(SYSCFG_CFGR2, 0x00000100);
g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR2), ==, 0x00000000);
}
static void test_set_only_bits(void)
{
/*
* Test that set only bits stay can't be cleared
*/
syscfg_writel(SYSCFG_CFGR2, 0x0000000F);
syscfg_writel(SYSCFG_CFGR2, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR2), ==, 0x0000000F);
syscfg_writel(SYSCFG_SWPR, 0xFFFFFFFF);
syscfg_writel(SYSCFG_SWPR, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_SWPR), ==, 0xFFFFFFFF);
syscfg_writel(SYSCFG_SWPR2, 0xFFFFFFFF);
syscfg_writel(SYSCFG_SWPR2, 0x00000000);
g_assert_cmpuint(syscfg_readl(SYSCFG_SWPR2), ==, 0xFFFFFFFF);
system_reset();
}
static void test_clear_only_bits(void)
{
/*
* Test that clear only bits stay can't be set
*/
syscfg_writel(SYSCFG_CFGR1, 0x00000000);
syscfg_writel(SYSCFG_CFGR1, 0x00000001);
g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR1), ==, 0x00000000);
system_reset();
}
static void test_interrupt(void)
{
/*
* Test that GPIO rising lines result in an irq
* with the right configuration
*/
qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
/* GPIOA is the default source for EXTI lines 0 to 15 */
syscfg_set_irq(0, 1);
g_assert_true(get_irq(0));
syscfg_set_irq(15, 1);
g_assert_true(get_irq(15));
/* Configure GPIOB[1] as the source input for EXTI1 */
syscfg_writel(SYSCFG_EXTICR1, 0x00000010);
syscfg_set_irq(17, 1);
g_assert_true(get_irq(1));
/* Clean the test */
syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
syscfg_set_irq(0, 0);
syscfg_set_irq(15, 0);
syscfg_set_irq(17, 0);
}
static void test_irq_pin_multiplexer(void)
{
/*
* Test that syscfg irq sets the right exti irq
*/
qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
syscfg_set_irq(0, 1);
/* Check that irq 0 was set and irq 15 wasn't */
g_assert_true(get_irq(0));
g_assert_false(get_irq(15));
/* Clean the test */
syscfg_set_irq(0, 0);
syscfg_set_irq(15, 1);
/* Check that irq 15 was set and irq 0 wasn't */
g_assert_true(get_irq(15));
g_assert_false(get_irq(0));
/* Clean the test */
syscfg_set_irq(15, 0);
}
static void test_irq_gpio_multiplexer(void)
{
/*
* Test that an irq is generated only by the right GPIO
*/
qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
/* GPIOA is the default source for EXTI lines 0 to 15 */
/* Check that setting rising pin GPIOA[0] generates an irq */
syscfg_set_irq(0, 1);
g_assert_true(get_irq(0));
/* Clean the test */
syscfg_set_irq(0, 0);
/* Check that setting rising pin GPIOB[0] doesn't generate an irq */
syscfg_set_irq(16, 1);
g_assert_false(get_irq(0));
/* Clean the test */
syscfg_set_irq(16, 0);
/* Configure GPIOB[0] as the source input for EXTI0 */
syscfg_writel(SYSCFG_EXTICR1, 0x00000001);
/* Check that setting rising pin GPIOA[0] doesn't generate an irq */
syscfg_set_irq(0, 1);
g_assert_false(get_irq(0));
/* Clean the test */
syscfg_set_irq(0, 0);
/* Check that setting rising pin GPIOB[0] generates an irq */
syscfg_set_irq(16, 1);
g_assert_true(get_irq(0));
/* Clean the test */
syscfg_set_irq(16, 0);
syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
}
int main(int argc, char **argv)
{
int ret;
g_test_init(&argc, &argv, NULL);
g_test_set_nonfatal_assertions();
qtest_add_func("stm32l4x5/syscfg/test_reset", test_reset);
qtest_add_func("stm32l4x5/syscfg/test_reserved_bits",
test_reserved_bits);
qtest_add_func("stm32l4x5/syscfg/test_set_and_clear",
test_set_and_clear);
qtest_add_func("stm32l4x5/syscfg/test_clear_by_writing_1",
test_clear_by_writing_1);
qtest_add_func("stm32l4x5/syscfg/test_set_only_bits",
test_set_only_bits);
qtest_add_func("stm32l4x5/syscfg/test_clear_only_bits",
test_clear_only_bits);
qtest_add_func("stm32l4x5/syscfg/test_interrupt",
test_interrupt);
qtest_add_func("stm32l4x5/syscfg/test_irq_pin_multiplexer",
test_irq_pin_multiplexer);
qtest_add_func("stm32l4x5/syscfg/test_irq_gpio_multiplexer",
test_irq_gpio_multiplexer);
qtest_start("-machine b-l475e-iot01a");
ret = g_test_run();
qtest_end();
return ret;
}