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target-arm: make IFSR banked

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When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFSR has a secure and a non-secure instance.  Adds IFSR32_EL2 definition and
storage.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-20-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Fabian Aggeler 2014-12-11 12:07:51 +00:00 • committed by Peter Maydell
parent 0c17d68c1d
commit 88ca1c2d70
2 changed files with 18 additions and 5 deletions
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10
target-arm/cpu.h
View file

@ -242,7 +242,15 @@ typedef struct CPUARMState {
uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
uint64_t hcr_el2; /* Hypervisor configuration register */
uint64_t scr_el3; /* Secure configuration register. */
uint32_t ifsr_el2; /* Fault status registers. */
union { /* Fault status registers. */
struct {
uint64_t ifsr_ns;
uint64_t ifsr_s;
};
struct {
uint64_t ifsr32_el2;
};
};
uint64_t esr_el[4];
uint32_t c6_region[8]; /* MPU base/size registers. */
uint64_t far_el[4]; /* Fault address registers. */