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target/riscv: Implement SGEIP bit in hip and hie CSRs

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A hypervisor can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-3-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel 2022-02-04 23:16:38 +05:30 • committed by Alistair Francis
parent dceecac8a2
commit 881df35d3d
3 changed files with 16 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

18
target/riscv/csr.c
View file

@ -461,12 +461,13 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
VS_MODE_INTERRUPTS;
static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
VS_MODE_INTERRUPTS;
HS_MODE_INTERRUPTS;
#define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
(1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
(1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
@ -748,7 +749,7 @@ static RISCVException write_mideleg(CPURISCVState *env, int csrno,
{
env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
if (riscv_has_ext(env, RVH)) {
env->mideleg |= VS_MODE_INTERRUPTS;
env->mideleg |= HS_MODE_INTERRUPTS;
}
return RISCV_EXCP_NONE;
}
@ -764,6 +765,9 @@ static RISCVException write_mie(CPURISCVState *env, int csrno,
target_ulong val)
{
env->mie = (env->mie & ~all_ints) | (val & all_ints);
if (!riscv_has_ext(env, RVH)) {
env->mie &= ~MIP_SGEIP;
}
return RISCV_EXCP_NONE;
}
@ -1110,7 +1114,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
}
if (ret_value) {
*ret_value &= env->mideleg;
*ret_value &= env->mideleg & S_MODE_INTERRUPTS;
}
return ret;
}
@ -1228,7 +1232,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
write_mask & hvip_writable_mask);
if (ret_value) {
*ret_value &= hvip_writable_mask;
*ret_value &= VS_MODE_INTERRUPTS;
}
return ret;
}
@ -1241,7 +1245,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
write_mask & hip_writable_mask);
if (ret_value) {
*ret_value &= hip_writable_mask;
*ret_value &= HS_MODE_INTERRUPTS;
}
return ret;
}
@ -1249,14 +1253,14 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
static RISCVException read_hie(CPURISCVState *env, int csrno,
target_ulong *val)
{
*val = env->mie & VS_MODE_INTERRUPTS;
*val = env->mie & HS_MODE_INTERRUPTS;
return RISCV_EXCP_NONE;
}
static RISCVException write_hie(CPURISCVState *env, int csrno,
target_ulong val)
{
target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS);
return write_mie(env, CSR_MIE, newval);
}