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target/riscv: Implement SGEIP bit in hip and hie CSRs

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A hypervisor can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-3-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel 2022-02-04 23:16:38 +05:30 • committed by Alistair Francis
parent dceecac8a2
commit 881df35d3d
3 changed files with 16 additions and 8 deletions
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3
target/riscv/cpu.c
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@ -434,6 +434,7 @@ static void riscv_cpu_reset(DeviceState *dev)
}
}
env->mcause = 0;
env->miclaim = MIP_SGEIP;
env->pc = env->resetvec;
env->two_stage_lookup = false;
/* mmte is supposed to have pm.current hardwired to 1 */
@ -695,7 +696,7 @@ static void riscv_cpu_init(Object *obj)
cpu_set_cpustate_pointers(cpu);
#ifndef CONFIG_USER_ONLY
qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
#endif /* CONFIG_USER_ONLY */
}