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target/arm: Simplify BFXIL expansion

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The mask implied by the extract is redundant with the one
implied by the deposit.  Also, fix spelling of BFXIL.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-05-23 14:47:43 +01:00 • committed by Peter Maydell
parent 80ac954c36
commit 87eb65a3c4
1 changed files with 3 additions and 3 deletions
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6
target/arm/translate-a64.c
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@ -4043,8 +4043,8 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
return; return;
} }
/* opc == 1, BXFIL fall through to deposit */ /* opc == 1, BFXIL fall through to deposit */
tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len); tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
pos = 0; pos = 0;
} else { } else {
/* Handle the ri > si case with a deposit /* Handle the ri > si case with a deposit
@ -4062,7 +4062,7 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
len = ri; len = ri;
} }
if (opc == 1) { /* BFM, BXFIL */ if (opc == 1) { /* BFM, BFXIL */
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
} else { } else {
/* SBFM or UBFM: We start with zero, and we haven't modified /* SBFM or UBFM: We start with zero, and we haven't modified