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target/arm: Vectorize USHL and SSHL
These instructions shift left or right depending on the sign of the input, and 7 bits are significant to the shift. This requires several masks and selects in addition to the actual shifts to form the complete answer. That said, the operation is still a small improvement even for two 64-bit elements -- 13 vector operations instead of 2 * 7 integer operations. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200216214232.4230-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
7abc8cabad
commit
87b74e8b6e
6 changed files with 389 additions and 66 deletions
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@ -3575,13 +3575,13 @@ static inline void gen_neon_shift_narrow(int size, TCGv_i32 var, TCGv_i32 shift,
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if (u) {
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switch (size) {
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case 1: gen_helper_neon_shl_u16(var, var, shift); break;
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case 2: gen_helper_neon_shl_u32(var, var, shift); break;
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case 2: gen_ushl_i32(var, var, shift); break;
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default: abort();
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}
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} else {
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switch (size) {
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case 1: gen_helper_neon_shl_s16(var, var, shift); break;
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case 2: gen_helper_neon_shl_s32(var, var, shift); break;
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case 2: gen_sshl_i32(var, var, shift); break;
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default: abort();
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}
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}
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@ -4384,6 +4384,280 @@ const GVecGen3 cmtst_op[4] = {
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.vece = MO_64 },
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};
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void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
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{
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TCGv_i32 lval = tcg_temp_new_i32();
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TCGv_i32 rval = tcg_temp_new_i32();
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TCGv_i32 lsh = tcg_temp_new_i32();
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TCGv_i32 rsh = tcg_temp_new_i32();
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TCGv_i32 zero = tcg_const_i32(0);
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TCGv_i32 max = tcg_const_i32(32);
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/*
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* Rely on the TCG guarantee that out of range shifts produce
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* unspecified results, not undefined behaviour (i.e. no trap).
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* Discard out-of-range results after the fact.
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*/
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tcg_gen_ext8s_i32(lsh, shift);
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tcg_gen_neg_i32(rsh, lsh);
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tcg_gen_shl_i32(lval, src, lsh);
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tcg_gen_shr_i32(rval, src, rsh);
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tcg_gen_movcond_i32(TCG_COND_LTU, dst, lsh, max, lval, zero);
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tcg_gen_movcond_i32(TCG_COND_LTU, dst, rsh, max, rval, dst);
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tcg_temp_free_i32(lval);
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tcg_temp_free_i32(rval);
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tcg_temp_free_i32(lsh);
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tcg_temp_free_i32(rsh);
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tcg_temp_free_i32(zero);
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tcg_temp_free_i32(max);
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}
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void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
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{
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TCGv_i64 lval = tcg_temp_new_i64();
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TCGv_i64 rval = tcg_temp_new_i64();
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TCGv_i64 lsh = tcg_temp_new_i64();
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TCGv_i64 rsh = tcg_temp_new_i64();
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TCGv_i64 zero = tcg_const_i64(0);
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TCGv_i64 max = tcg_const_i64(64);
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/*
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* Rely on the TCG guarantee that out of range shifts produce
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* unspecified results, not undefined behaviour (i.e. no trap).
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* Discard out-of-range results after the fact.
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*/
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tcg_gen_ext8s_i64(lsh, shift);
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tcg_gen_neg_i64(rsh, lsh);
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tcg_gen_shl_i64(lval, src, lsh);
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tcg_gen_shr_i64(rval, src, rsh);
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tcg_gen_movcond_i64(TCG_COND_LTU, dst, lsh, max, lval, zero);
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tcg_gen_movcond_i64(TCG_COND_LTU, dst, rsh, max, rval, dst);
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tcg_temp_free_i64(lval);
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tcg_temp_free_i64(rval);
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tcg_temp_free_i64(lsh);
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tcg_temp_free_i64(rsh);
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tcg_temp_free_i64(zero);
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tcg_temp_free_i64(max);
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}
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static void gen_ushl_vec(unsigned vece, TCGv_vec dst,
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TCGv_vec src, TCGv_vec shift)
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{
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TCGv_vec lval = tcg_temp_new_vec_matching(dst);
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TCGv_vec rval = tcg_temp_new_vec_matching(dst);
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TCGv_vec lsh = tcg_temp_new_vec_matching(dst);
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TCGv_vec rsh = tcg_temp_new_vec_matching(dst);
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TCGv_vec msk, max;
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tcg_gen_neg_vec(vece, rsh, shift);
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if (vece == MO_8) {
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tcg_gen_mov_vec(lsh, shift);
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} else {
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msk = tcg_temp_new_vec_matching(dst);
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tcg_gen_dupi_vec(vece, msk, 0xff);
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tcg_gen_and_vec(vece, lsh, shift, msk);
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tcg_gen_and_vec(vece, rsh, rsh, msk);
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tcg_temp_free_vec(msk);
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}
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/*
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* Rely on the TCG guarantee that out of range shifts produce
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* unspecified results, not undefined behaviour (i.e. no trap).
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* Discard out-of-range results after the fact.
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*/
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tcg_gen_shlv_vec(vece, lval, src, lsh);
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tcg_gen_shrv_vec(vece, rval, src, rsh);
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max = tcg_temp_new_vec_matching(dst);
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tcg_gen_dupi_vec(vece, max, 8 << vece);
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/*
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* The choice of LT (signed) and GEU (unsigned) are biased toward
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* the instructions of the x86_64 host. For MO_8, the whole byte
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* is significant so we must use an unsigned compare; otherwise we
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* have already masked to a byte and so a signed compare works.
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* Other tcg hosts have a full set of comparisons and do not care.
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*/
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if (vece == MO_8) {
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tcg_gen_cmp_vec(TCG_COND_GEU, vece, lsh, lsh, max);
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tcg_gen_cmp_vec(TCG_COND_GEU, vece, rsh, rsh, max);
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tcg_gen_andc_vec(vece, lval, lval, lsh);
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tcg_gen_andc_vec(vece, rval, rval, rsh);
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} else {
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tcg_gen_cmp_vec(TCG_COND_LT, vece, lsh, lsh, max);
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tcg_gen_cmp_vec(TCG_COND_LT, vece, rsh, rsh, max);
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tcg_gen_and_vec(vece, lval, lval, lsh);
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tcg_gen_and_vec(vece, rval, rval, rsh);
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}
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tcg_gen_or_vec(vece, dst, lval, rval);
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tcg_temp_free_vec(max);
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tcg_temp_free_vec(lval);
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tcg_temp_free_vec(rval);
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tcg_temp_free_vec(lsh);
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tcg_temp_free_vec(rsh);
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}
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static const TCGOpcode ushl_list[] = {
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INDEX_op_neg_vec, INDEX_op_shlv_vec,
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INDEX_op_shrv_vec, INDEX_op_cmp_vec, 0
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};
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const GVecGen3 ushl_op[4] = {
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{ .fniv = gen_ushl_vec,
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.fno = gen_helper_gvec_ushl_b,
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.opt_opc = ushl_list,
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.vece = MO_8 },
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{ .fniv = gen_ushl_vec,
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.fno = gen_helper_gvec_ushl_h,
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.opt_opc = ushl_list,
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.vece = MO_16 },
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{ .fni4 = gen_ushl_i32,
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.fniv = gen_ushl_vec,
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.opt_opc = ushl_list,
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.vece = MO_32 },
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{ .fni8 = gen_ushl_i64,
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.fniv = gen_ushl_vec,
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.opt_opc = ushl_list,
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.vece = MO_64 },
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};
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void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
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{
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TCGv_i32 lval = tcg_temp_new_i32();
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TCGv_i32 rval = tcg_temp_new_i32();
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TCGv_i32 lsh = tcg_temp_new_i32();
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TCGv_i32 rsh = tcg_temp_new_i32();
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TCGv_i32 zero = tcg_const_i32(0);
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TCGv_i32 max = tcg_const_i32(31);
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/*
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* Rely on the TCG guarantee that out of range shifts produce
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* unspecified results, not undefined behaviour (i.e. no trap).
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* Discard out-of-range results after the fact.
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*/
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tcg_gen_ext8s_i32(lsh, shift);
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tcg_gen_neg_i32(rsh, lsh);
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tcg_gen_shl_i32(lval, src, lsh);
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tcg_gen_umin_i32(rsh, rsh, max);
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tcg_gen_sar_i32(rval, src, rsh);
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tcg_gen_movcond_i32(TCG_COND_LEU, lval, lsh, max, lval, zero);
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tcg_gen_movcond_i32(TCG_COND_LT, dst, lsh, zero, rval, lval);
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tcg_temp_free_i32(lval);
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tcg_temp_free_i32(rval);
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tcg_temp_free_i32(lsh);
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tcg_temp_free_i32(rsh);
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tcg_temp_free_i32(zero);
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tcg_temp_free_i32(max);
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}
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void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
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{
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TCGv_i64 lval = tcg_temp_new_i64();
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TCGv_i64 rval = tcg_temp_new_i64();
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TCGv_i64 lsh = tcg_temp_new_i64();
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TCGv_i64 rsh = tcg_temp_new_i64();
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TCGv_i64 zero = tcg_const_i64(0);
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TCGv_i64 max = tcg_const_i64(63);
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/*
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* Rely on the TCG guarantee that out of range shifts produce
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* unspecified results, not undefined behaviour (i.e. no trap).
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* Discard out-of-range results after the fact.
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*/
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tcg_gen_ext8s_i64(lsh, shift);
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tcg_gen_neg_i64(rsh, lsh);
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tcg_gen_shl_i64(lval, src, lsh);
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tcg_gen_umin_i64(rsh, rsh, max);
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tcg_gen_sar_i64(rval, src, rsh);
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tcg_gen_movcond_i64(TCG_COND_LEU, lval, lsh, max, lval, zero);
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tcg_gen_movcond_i64(TCG_COND_LT, dst, lsh, zero, rval, lval);
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tcg_temp_free_i64(lval);
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tcg_temp_free_i64(rval);
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tcg_temp_free_i64(lsh);
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tcg_temp_free_i64(rsh);
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tcg_temp_free_i64(zero);
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tcg_temp_free_i64(max);
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}
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static void gen_sshl_vec(unsigned vece, TCGv_vec dst,
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TCGv_vec src, TCGv_vec shift)
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{
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TCGv_vec lval = tcg_temp_new_vec_matching(dst);
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TCGv_vec rval = tcg_temp_new_vec_matching(dst);
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TCGv_vec lsh = tcg_temp_new_vec_matching(dst);
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TCGv_vec rsh = tcg_temp_new_vec_matching(dst);
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TCGv_vec tmp = tcg_temp_new_vec_matching(dst);
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/*
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* Rely on the TCG guarantee that out of range shifts produce
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* unspecified results, not undefined behaviour (i.e. no trap).
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* Discard out-of-range results after the fact.
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*/
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tcg_gen_neg_vec(vece, rsh, shift);
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if (vece == MO_8) {
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tcg_gen_mov_vec(lsh, shift);
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} else {
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tcg_gen_dupi_vec(vece, tmp, 0xff);
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tcg_gen_and_vec(vece, lsh, shift, tmp);
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tcg_gen_and_vec(vece, rsh, rsh, tmp);
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}
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/* Bound rsh so out of bound right shift gets -1. */
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tcg_gen_dupi_vec(vece, tmp, (8 << vece) - 1);
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tcg_gen_umin_vec(vece, rsh, rsh, tmp);
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tcg_gen_cmp_vec(TCG_COND_GT, vece, tmp, lsh, tmp);
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tcg_gen_shlv_vec(vece, lval, src, lsh);
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tcg_gen_sarv_vec(vece, rval, src, rsh);
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/* Select in-bound left shift. */
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tcg_gen_andc_vec(vece, lval, lval, tmp);
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/* Select between left and right shift. */
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if (vece == MO_8) {
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tcg_gen_dupi_vec(vece, tmp, 0);
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tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, tmp, rval, lval);
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} else {
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tcg_gen_dupi_vec(vece, tmp, 0x80);
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tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, tmp, lval, rval);
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}
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tcg_temp_free_vec(lval);
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tcg_temp_free_vec(rval);
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tcg_temp_free_vec(lsh);
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tcg_temp_free_vec(rsh);
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tcg_temp_free_vec(tmp);
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}
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static const TCGOpcode sshl_list[] = {
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INDEX_op_neg_vec, INDEX_op_umin_vec, INDEX_op_shlv_vec,
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INDEX_op_sarv_vec, INDEX_op_cmp_vec, INDEX_op_cmpsel_vec, 0
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};
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const GVecGen3 sshl_op[4] = {
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{ .fniv = gen_sshl_vec,
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.fno = gen_helper_gvec_sshl_b,
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.opt_opc = sshl_list,
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.vece = MO_8 },
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{ .fniv = gen_sshl_vec,
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.fno = gen_helper_gvec_sshl_h,
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.opt_opc = sshl_list,
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.vece = MO_16 },
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{ .fni4 = gen_sshl_i32,
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.fniv = gen_sshl_vec,
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.opt_opc = sshl_list,
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.vece = MO_32 },
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{ .fni8 = gen_sshl_i64,
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.fniv = gen_sshl_vec,
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.opt_opc = sshl_list,
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.vece = MO_64 },
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};
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static void gen_uqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,
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TCGv_vec a, TCGv_vec b)
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{
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@ -4787,6 +5061,12 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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vec_size, vec_size);
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}
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return 0;
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case NEON_3R_VSHL:
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/* Note the operation is vshl vd,vm,vn */
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tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
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u ? &ushl_op[size] : &sshl_op[size]);
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return 0;
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}
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if (size == 3) {
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@ -4795,13 +5075,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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neon_load_reg64(cpu_V0, rn + pass);
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neon_load_reg64(cpu_V1, rm + pass);
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switch (op) {
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case NEON_3R_VSHL:
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if (u) {
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gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
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} else {
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gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
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}
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break;
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case NEON_3R_VQSHL:
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if (u) {
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gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
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@ -4836,7 +5109,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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}
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pairwise = 0;
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switch (op) {
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case NEON_3R_VSHL:
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case NEON_3R_VQSHL:
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case NEON_3R_VRSHL:
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case NEON_3R_VQRSHL:
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@ -4916,9 +5188,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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case NEON_3R_VHSUB:
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GEN_NEON_INTEGER_OP(hsub);
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break;
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case NEON_3R_VSHL:
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GEN_NEON_INTEGER_OP(shl);
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break;
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case NEON_3R_VQSHL:
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GEN_NEON_INTEGER_OP_ENV(qshl);
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break;
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@ -5327,9 +5596,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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}
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} else {
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if (input_unsigned) {
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gen_helper_neon_shl_u64(cpu_V0, in, tmp64);
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gen_ushl_i64(cpu_V0, in, tmp64);
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} else {
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gen_helper_neon_shl_s64(cpu_V0, in, tmp64);
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gen_sshl_i64(cpu_V0, in, tmp64);
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}
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}
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tmp = tcg_temp_new_i32();
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