mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-11 03:24:58 -06:00
hw/arm/fsl-imx8mp: Implement clock tree
Fixes quite a few stack traces during the Linux boot process. Also provides the clocks for devices added later, e.g. enet1. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-6-shentey@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Bernhard Beschow
Peter Maydell
parent
a4eefc69b2
commit
86c2dff955
11 changed files with 483 additions and 0 deletions
|
|
@ -826,7 +826,9 @@ L: qemu-arm@nongnu.org
|
||||||
S: Maintained
|
S: Maintained
|
||||||
F: hw/arm/imx8mp-evk.c
|
F: hw/arm/imx8mp-evk.c
|
||||||
F: hw/arm/fsl-imx8mp.c
|
F: hw/arm/fsl-imx8mp.c
|
||||||
|
F: hw/misc/imx8mp_*.c
|
||||||
F: include/hw/arm/fsl-imx8mp.h
|
F: include/hw/arm/fsl-imx8mp.h
|
||||||
|
F: include/hw/misc/imx8mp_*.h
|
||||||
F: docs/system/arm/imx8mp-evk.rst
|
F: docs/system/arm/imx8mp-evk.rst
|
||||||
|
|
||||||
MPS2 / MPS3
|
MPS2 / MPS3
|
||||||
|
|
|
||||||
|
|
@ -12,6 +12,7 @@ The ``imx8mp-evk`` machine implements the following devices:
|
||||||
* Up to 4 Cortex-A53 cores
|
* Up to 4 Cortex-A53 cores
|
||||||
* Generic Interrupt Controller (GICv3)
|
* Generic Interrupt Controller (GICv3)
|
||||||
* 4 UARTs
|
* 4 UARTs
|
||||||
|
* Clock Tree
|
||||||
|
|
||||||
Boot options
|
Boot options
|
||||||
------------
|
------------
|
||||||
|
|
|
||||||
|
|
@ -596,6 +596,8 @@ config FSL_IMX7
|
||||||
config FSL_IMX8MP
|
config FSL_IMX8MP
|
||||||
bool
|
bool
|
||||||
select ARM_GIC
|
select ARM_GIC
|
||||||
|
select FSL_IMX8MP_ANALOG
|
||||||
|
select FSL_IMX8MP_CCM
|
||||||
select IMX
|
select IMX
|
||||||
select UNIMP
|
select UNIMP
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -197,6 +197,10 @@ static void fsl_imx8mp_init(Object *obj)
|
||||||
|
|
||||||
object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GICV3);
|
object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GICV3);
|
||||||
|
|
||||||
|
object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX8MP_CCM);
|
||||||
|
|
||||||
|
object_initialize_child(obj, "analog", &s->analog, TYPE_IMX8MP_ANALOG);
|
||||||
|
|
||||||
for (i = 0; i < FSL_IMX8MP_NUM_UARTS; i++) {
|
for (i = 0; i < FSL_IMX8MP_NUM_UARTS; i++) {
|
||||||
g_autofree char *name = g_strdup_printf("uart%d", i + 1);
|
g_autofree char *name = g_strdup_printf("uart%d", i + 1);
|
||||||
object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
|
object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
|
||||||
|
|
@ -304,6 +308,20 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* CCM */
|
||||||
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0,
|
||||||
|
fsl_imx8mp_memmap[FSL_IMX8MP_CCM].addr);
|
||||||
|
|
||||||
|
/* Analog */
|
||||||
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->analog), errp)) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0,
|
||||||
|
fsl_imx8mp_memmap[FSL_IMX8MP_ANA_PLL].addr);
|
||||||
|
|
||||||
/* UARTs */
|
/* UARTs */
|
||||||
for (i = 0; i < FSL_IMX8MP_NUM_UARTS; i++) {
|
for (i = 0; i < FSL_IMX8MP_NUM_UARTS; i++) {
|
||||||
struct {
|
struct {
|
||||||
|
|
@ -329,6 +347,8 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
|
||||||
/* Unimplemented devices */
|
/* Unimplemented devices */
|
||||||
for (i = 0; i < ARRAY_SIZE(fsl_imx8mp_memmap); i++) {
|
for (i = 0; i < ARRAY_SIZE(fsl_imx8mp_memmap); i++) {
|
||||||
switch (i) {
|
switch (i) {
|
||||||
|
case FSL_IMX8MP_ANA_PLL:
|
||||||
|
case FSL_IMX8MP_CCM:
|
||||||
case FSL_IMX8MP_GIC_DIST:
|
case FSL_IMX8MP_GIC_DIST:
|
||||||
case FSL_IMX8MP_GIC_REDIST:
|
case FSL_IMX8MP_GIC_REDIST:
|
||||||
case FSL_IMX8MP_RAM:
|
case FSL_IMX8MP_RAM:
|
||||||
|
|
|
||||||
|
|
@ -78,6 +78,12 @@ config IMX
|
||||||
select SSI
|
select SSI
|
||||||
select USB_EHCI_SYSBUS
|
select USB_EHCI_SYSBUS
|
||||||
|
|
||||||
|
config FSL_IMX8MP_ANALOG
|
||||||
|
bool
|
||||||
|
|
||||||
|
config FSL_IMX8MP_CCM
|
||||||
|
bool
|
||||||
|
|
||||||
config STM32_RCC
|
config STM32_RCC
|
||||||
bool
|
bool
|
||||||
|
|
||||||
|
|
|
||||||
160
hw/misc/imx8mp_analog.c
Normal file
160
hw/misc/imx8mp_analog.c
Normal file
|
|
@ -0,0 +1,160 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2025 Bernhard Beschow <shentey@gmail.com>
|
||||||
|
*
|
||||||
|
* i.MX 8M Plus ANALOG IP block emulation code
|
||||||
|
*
|
||||||
|
* Based on hw/misc/imx7_ccm.c
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "qemu/osdep.h"
|
||||||
|
#include "qemu/log.h"
|
||||||
|
|
||||||
|
#include "hw/misc/imx8mp_analog.h"
|
||||||
|
#include "migration/vmstate.h"
|
||||||
|
|
||||||
|
#define ANALOG_PLL_LOCK BIT(31)
|
||||||
|
|
||||||
|
static void imx8mp_analog_reset(DeviceState *dev)
|
||||||
|
{
|
||||||
|
IMX8MPAnalogState *s = IMX8MP_ANALOG(dev);
|
||||||
|
|
||||||
|
memset(s->analog, 0, sizeof(s->analog));
|
||||||
|
|
||||||
|
s->analog[ANALOG_AUDIO_PLL1_GEN_CTRL] = 0x00002010;
|
||||||
|
s->analog[ANALOG_AUDIO_PLL1_FDIV_CTL0] = 0x00145032;
|
||||||
|
s->analog[ANALOG_AUDIO_PLL1_FDIV_CTL1] = 0x00000000;
|
||||||
|
s->analog[ANALOG_AUDIO_PLL1_SSCG_CTRL] = 0x00000000;
|
||||||
|
s->analog[ANALOG_AUDIO_PLL1_MNIT_CTRL] = 0x00100103;
|
||||||
|
s->analog[ANALOG_AUDIO_PLL2_GEN_CTRL] = 0x00002010;
|
||||||
|
s->analog[ANALOG_AUDIO_PLL2_FDIV_CTL0] = 0x00145032;
|
||||||
|
s->analog[ANALOG_AUDIO_PLL2_FDIV_CTL1] = 0x00000000;
|
||||||
|
s->analog[ANALOG_AUDIO_PLL2_SSCG_CTRL] = 0x00000000;
|
||||||
|
s->analog[ANALOG_AUDIO_PLL2_MNIT_CTRL] = 0x00100103;
|
||||||
|
s->analog[ANALOG_VIDEO_PLL1_GEN_CTRL] = 0x00002010;
|
||||||
|
s->analog[ANALOG_VIDEO_PLL1_FDIV_CTL0] = 0x00145032;
|
||||||
|
s->analog[ANALOG_VIDEO_PLL1_FDIV_CTL1] = 0x00000000;
|
||||||
|
s->analog[ANALOG_VIDEO_PLL1_SSCG_CTRL] = 0x00000000;
|
||||||
|
s->analog[ANALOG_VIDEO_PLL1_MNIT_CTRL] = 0x00100103;
|
||||||
|
s->analog[ANALOG_DRAM_PLL_GEN_CTRL] = 0x00002010;
|
||||||
|
s->analog[ANALOG_DRAM_PLL_FDIV_CTL0] = 0x0012c032;
|
||||||
|
s->analog[ANALOG_DRAM_PLL_FDIV_CTL1] = 0x00000000;
|
||||||
|
s->analog[ANALOG_DRAM_PLL_SSCG_CTRL] = 0x00000000;
|
||||||
|
s->analog[ANALOG_DRAM_PLL_MNIT_CTRL] = 0x00100103;
|
||||||
|
s->analog[ANALOG_GPU_PLL_GEN_CTRL] = 0x00000810;
|
||||||
|
s->analog[ANALOG_GPU_PLL_FDIV_CTL0] = 0x000c8031;
|
||||||
|
s->analog[ANALOG_GPU_PLL_LOCKD_CTRL] = 0x0010003f;
|
||||||
|
s->analog[ANALOG_GPU_PLL_MNIT_CTRL] = 0x00280081;
|
||||||
|
s->analog[ANALOG_VPU_PLL_GEN_CTRL] = 0x00000810;
|
||||||
|
s->analog[ANALOG_VPU_PLL_FDIV_CTL0] = 0x0012c032;
|
||||||
|
s->analog[ANALOG_VPU_PLL_LOCKD_CTRL] = 0x0010003f;
|
||||||
|
s->analog[ANALOG_VPU_PLL_MNIT_CTRL] = 0x00280081;
|
||||||
|
s->analog[ANALOG_ARM_PLL_GEN_CTRL] = 0x00000810;
|
||||||
|
s->analog[ANALOG_ARM_PLL_FDIV_CTL0] = 0x000fa031;
|
||||||
|
s->analog[ANALOG_ARM_PLL_LOCKD_CTRL] = 0x0010003f;
|
||||||
|
s->analog[ANALOG_ARM_PLL_MNIT_CTRL] = 0x00280081;
|
||||||
|
s->analog[ANALOG_SYS_PLL1_GEN_CTRL] = 0x0aaaa810;
|
||||||
|
s->analog[ANALOG_SYS_PLL1_FDIV_CTL0] = 0x00190032;
|
||||||
|
s->analog[ANALOG_SYS_PLL1_LOCKD_CTRL] = 0x0010003f;
|
||||||
|
s->analog[ANALOG_SYS_PLL1_MNIT_CTRL] = 0x00280081;
|
||||||
|
s->analog[ANALOG_SYS_PLL2_GEN_CTRL] = 0x0aaaa810;
|
||||||
|
s->analog[ANALOG_SYS_PLL2_FDIV_CTL0] = 0x000fa031;
|
||||||
|
s->analog[ANALOG_SYS_PLL2_LOCKD_CTRL] = 0x0010003f;
|
||||||
|
s->analog[ANALOG_SYS_PLL2_MNIT_CTRL] = 0x00280081;
|
||||||
|
s->analog[ANALOG_SYS_PLL3_GEN_CTRL] = 0x00000810;
|
||||||
|
s->analog[ANALOG_SYS_PLL3_FDIV_CTL0] = 0x000fa031;
|
||||||
|
s->analog[ANALOG_SYS_PLL3_LOCKD_CTRL] = 0x0010003f;
|
||||||
|
s->analog[ANALOG_SYS_PLL3_MNIT_CTRL] = 0x00280081;
|
||||||
|
s->analog[ANALOG_OSC_MISC_CFG] = 0x00000000;
|
||||||
|
s->analog[ANALOG_ANAMIX_PLL_MNIT_CTL] = 0x00000000;
|
||||||
|
s->analog[ANALOG_DIGPROG] = 0x00824010;
|
||||||
|
|
||||||
|
/* all PLLs need to be locked */
|
||||||
|
s->analog[ANALOG_AUDIO_PLL1_GEN_CTRL] |= ANALOG_PLL_LOCK;
|
||||||
|
s->analog[ANALOG_AUDIO_PLL2_GEN_CTRL] |= ANALOG_PLL_LOCK;
|
||||||
|
s->analog[ANALOG_VIDEO_PLL1_GEN_CTRL] |= ANALOG_PLL_LOCK;
|
||||||
|
s->analog[ANALOG_DRAM_PLL_GEN_CTRL] |= ANALOG_PLL_LOCK;
|
||||||
|
s->analog[ANALOG_GPU_PLL_GEN_CTRL] |= ANALOG_PLL_LOCK;
|
||||||
|
s->analog[ANALOG_VPU_PLL_GEN_CTRL] |= ANALOG_PLL_LOCK;
|
||||||
|
s->analog[ANALOG_ARM_PLL_GEN_CTRL] |= ANALOG_PLL_LOCK;
|
||||||
|
s->analog[ANALOG_SYS_PLL1_GEN_CTRL] |= ANALOG_PLL_LOCK;
|
||||||
|
s->analog[ANALOG_SYS_PLL2_GEN_CTRL] |= ANALOG_PLL_LOCK;
|
||||||
|
s->analog[ANALOG_SYS_PLL3_GEN_CTRL] |= ANALOG_PLL_LOCK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint64_t imx8mp_analog_read(void *opaque, hwaddr offset, unsigned size)
|
||||||
|
{
|
||||||
|
IMX8MPAnalogState *s = opaque;
|
||||||
|
|
||||||
|
return s->analog[offset >> 2];
|
||||||
|
}
|
||||||
|
|
||||||
|
static void imx8mp_analog_write(void *opaque, hwaddr offset,
|
||||||
|
uint64_t value, unsigned size)
|
||||||
|
{
|
||||||
|
IMX8MPAnalogState *s = opaque;
|
||||||
|
|
||||||
|
if (offset >> 2 == ANALOG_DIGPROG) {
|
||||||
|
qemu_log_mask(LOG_GUEST_ERROR,
|
||||||
|
"Guest write to read-only ANALOG_DIGPROG register\n");
|
||||||
|
} else {
|
||||||
|
s->analog[offset >> 2] = value;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct MemoryRegionOps imx8mp_analog_ops = {
|
||||||
|
.read = imx8mp_analog_read,
|
||||||
|
.write = imx8mp_analog_write,
|
||||||
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||||
|
.impl = {
|
||||||
|
.min_access_size = 4,
|
||||||
|
.max_access_size = 4,
|
||||||
|
.unaligned = false,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static void imx8mp_analog_init(Object *obj)
|
||||||
|
{
|
||||||
|
IMX8MPAnalogState *s = IMX8MP_ANALOG(obj);
|
||||||
|
SysBusDevice *sd = SYS_BUS_DEVICE(obj);
|
||||||
|
|
||||||
|
memory_region_init(&s->mmio.container, obj, TYPE_IMX8MP_ANALOG, 0x10000);
|
||||||
|
|
||||||
|
memory_region_init_io(&s->mmio.analog, obj, &imx8mp_analog_ops, s,
|
||||||
|
TYPE_IMX8MP_ANALOG, sizeof(s->analog));
|
||||||
|
memory_region_add_subregion(&s->mmio.container, 0, &s->mmio.analog);
|
||||||
|
|
||||||
|
sysbus_init_mmio(sd, &s->mmio.container);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const VMStateDescription imx8mp_analog_vmstate = {
|
||||||
|
.name = TYPE_IMX8MP_ANALOG,
|
||||||
|
.version_id = 1,
|
||||||
|
.minimum_version_id = 1,
|
||||||
|
.fields = (const VMStateField[]) {
|
||||||
|
VMSTATE_UINT32_ARRAY(analog, IMX8MPAnalogState, ANALOG_MAX),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static void imx8mp_analog_class_init(ObjectClass *klass, void *data)
|
||||||
|
{
|
||||||
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||||
|
|
||||||
|
device_class_set_legacy_reset(dc, imx8mp_analog_reset);
|
||||||
|
dc->vmsd = &imx8mp_analog_vmstate;
|
||||||
|
dc->desc = "i.MX 8M Plus Analog Module";
|
||||||
|
}
|
||||||
|
|
||||||
|
static const TypeInfo imx8mp_analog_types[] = {
|
||||||
|
{
|
||||||
|
.name = TYPE_IMX8MP_ANALOG,
|
||||||
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||||||
|
.instance_size = sizeof(IMX8MPAnalogState),
|
||||||
|
.instance_init = imx8mp_analog_init,
|
||||||
|
.class_init = imx8mp_analog_class_init,
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
DEFINE_TYPES(imx8mp_analog_types);
|
||||||
175
hw/misc/imx8mp_ccm.c
Normal file
175
hw/misc/imx8mp_ccm.c
Normal file
|
|
@ -0,0 +1,175 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2025 Bernhard Beschow <shentey@gmail.com>
|
||||||
|
*
|
||||||
|
* i.MX 8M Plus CCM IP block emulation code
|
||||||
|
*
|
||||||
|
* Based on hw/misc/imx7_ccm.c
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "qemu/osdep.h"
|
||||||
|
#include "qemu/log.h"
|
||||||
|
|
||||||
|
#include "hw/misc/imx8mp_ccm.h"
|
||||||
|
#include "migration/vmstate.h"
|
||||||
|
|
||||||
|
#include "trace.h"
|
||||||
|
|
||||||
|
#define CKIH_FREQ 16000000 /* 16MHz crystal input */
|
||||||
|
|
||||||
|
static void imx8mp_ccm_reset(DeviceState *dev)
|
||||||
|
{
|
||||||
|
IMX8MPCCMState *s = IMX8MP_CCM(dev);
|
||||||
|
|
||||||
|
memset(s->ccm, 0, sizeof(s->ccm));
|
||||||
|
}
|
||||||
|
|
||||||
|
#define CCM_INDEX(offset) (((offset) & ~(hwaddr)0xF) / sizeof(uint32_t))
|
||||||
|
#define CCM_BITOP(offset) ((offset) & (hwaddr)0xF)
|
||||||
|
|
||||||
|
enum {
|
||||||
|
CCM_BITOP_NONE = 0x00,
|
||||||
|
CCM_BITOP_SET = 0x04,
|
||||||
|
CCM_BITOP_CLR = 0x08,
|
||||||
|
CCM_BITOP_TOG = 0x0C,
|
||||||
|
};
|
||||||
|
|
||||||
|
static uint64_t imx8mp_set_clr_tog_read(void *opaque, hwaddr offset,
|
||||||
|
unsigned size)
|
||||||
|
{
|
||||||
|
const uint32_t *mmio = opaque;
|
||||||
|
|
||||||
|
return mmio[CCM_INDEX(offset)];
|
||||||
|
}
|
||||||
|
|
||||||
|
static void imx8mp_set_clr_tog_write(void *opaque, hwaddr offset,
|
||||||
|
uint64_t value, unsigned size)
|
||||||
|
{
|
||||||
|
const uint8_t bitop = CCM_BITOP(offset);
|
||||||
|
const uint32_t index = CCM_INDEX(offset);
|
||||||
|
uint32_t *mmio = opaque;
|
||||||
|
|
||||||
|
switch (bitop) {
|
||||||
|
case CCM_BITOP_NONE:
|
||||||
|
mmio[index] = value;
|
||||||
|
break;
|
||||||
|
case CCM_BITOP_SET:
|
||||||
|
mmio[index] |= value;
|
||||||
|
break;
|
||||||
|
case CCM_BITOP_CLR:
|
||||||
|
mmio[index] &= ~value;
|
||||||
|
break;
|
||||||
|
case CCM_BITOP_TOG:
|
||||||
|
mmio[index] ^= value;
|
||||||
|
break;
|
||||||
|
};
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct MemoryRegionOps imx8mp_set_clr_tog_ops = {
|
||||||
|
.read = imx8mp_set_clr_tog_read,
|
||||||
|
.write = imx8mp_set_clr_tog_write,
|
||||||
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||||
|
.impl = {
|
||||||
|
/*
|
||||||
|
* Our device would not work correctly if the guest was doing
|
||||||
|
* unaligned access. This might not be a limitation on the real
|
||||||
|
* device but in practice there is no reason for a guest to access
|
||||||
|
* this device unaligned.
|
||||||
|
*/
|
||||||
|
.min_access_size = 4,
|
||||||
|
.max_access_size = 4,
|
||||||
|
.unaligned = false,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static void imx8mp_ccm_init(Object *obj)
|
||||||
|
{
|
||||||
|
SysBusDevice *sd = SYS_BUS_DEVICE(obj);
|
||||||
|
IMX8MPCCMState *s = IMX8MP_CCM(obj);
|
||||||
|
|
||||||
|
memory_region_init_io(&s->iomem,
|
||||||
|
obj,
|
||||||
|
&imx8mp_set_clr_tog_ops,
|
||||||
|
s->ccm,
|
||||||
|
TYPE_IMX8MP_CCM ".ccm",
|
||||||
|
sizeof(s->ccm));
|
||||||
|
|
||||||
|
sysbus_init_mmio(sd, &s->iomem);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const VMStateDescription imx8mp_ccm_vmstate = {
|
||||||
|
.name = TYPE_IMX8MP_CCM,
|
||||||
|
.version_id = 1,
|
||||||
|
.minimum_version_id = 1,
|
||||||
|
.fields = (const VMStateField[]) {
|
||||||
|
VMSTATE_UINT32_ARRAY(ccm, IMX8MPCCMState, CCM_MAX),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static uint32_t imx8mp_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* This function is "consumed" by GPT emulation code. Some clocks
|
||||||
|
* have fixed frequencies and we can provide requested frequency
|
||||||
|
* easily. However for CCM provided clocks (like IPG) each GPT
|
||||||
|
* timer can have its own clock root.
|
||||||
|
* This means we need additional information when calling this
|
||||||
|
* function to know the requester's identity.
|
||||||
|
*/
|
||||||
|
uint32_t freq = 0;
|
||||||
|
|
||||||
|
switch (clock) {
|
||||||
|
case CLK_NONE:
|
||||||
|
break;
|
||||||
|
case CLK_32k:
|
||||||
|
freq = CKIL_FREQ;
|
||||||
|
break;
|
||||||
|
case CLK_HIGH:
|
||||||
|
freq = CKIH_FREQ;
|
||||||
|
break;
|
||||||
|
case CLK_IPG:
|
||||||
|
case CLK_IPG_HIGH:
|
||||||
|
/*
|
||||||
|
* For now we don't have a way to figure out the device this
|
||||||
|
* function is called for. Until then the IPG derived clocks
|
||||||
|
* are left unimplemented.
|
||||||
|
*/
|
||||||
|
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Clock %d Not implemented\n",
|
||||||
|
TYPE_IMX8MP_CCM, __func__, clock);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
|
||||||
|
TYPE_IMX8MP_CCM, __func__, clock);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
trace_ccm_clock_freq(clock, freq);
|
||||||
|
|
||||||
|
return freq;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void imx8mp_ccm_class_init(ObjectClass *klass, void *data)
|
||||||
|
{
|
||||||
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||||
|
IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
|
||||||
|
|
||||||
|
device_class_set_legacy_reset(dc, imx8mp_ccm_reset);
|
||||||
|
dc->vmsd = &imx8mp_ccm_vmstate;
|
||||||
|
dc->desc = "i.MX 8M Plus Clock Control Module";
|
||||||
|
|
||||||
|
ccm->get_clock_frequency = imx8mp_ccm_get_clock_frequency;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const TypeInfo imx8mp_ccm_types[] = {
|
||||||
|
{
|
||||||
|
.name = TYPE_IMX8MP_CCM,
|
||||||
|
.parent = TYPE_IMX_CCM,
|
||||||
|
.instance_size = sizeof(IMX8MPCCMState),
|
||||||
|
.instance_init = imx8mp_ccm_init,
|
||||||
|
.class_init = imx8mp_ccm_class_init,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
DEFINE_TYPES(imx8mp_ccm_types);
|
||||||
|
|
@ -55,6 +55,8 @@ system_ss.add(when: 'CONFIG_AXP2XX_PMU', if_true: files('axp2xx.c'))
|
||||||
system_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c'))
|
system_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c'))
|
||||||
system_ss.add(when: 'CONFIG_ECCMEMCTL', if_true: files('eccmemctl.c'))
|
system_ss.add(when: 'CONFIG_ECCMEMCTL', if_true: files('eccmemctl.c'))
|
||||||
system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_pmu.c', 'exynos4210_clk.c', 'exynos4210_rng.c'))
|
system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_pmu.c', 'exynos4210_clk.c', 'exynos4210_rng.c'))
|
||||||
|
system_ss.add(when: 'CONFIG_FSL_IMX8MP_ANALOG', if_true: files('imx8mp_analog.c'))
|
||||||
|
system_ss.add(when: 'CONFIG_FSL_IMX8MP_CCM', if_true: files('imx8mp_ccm.c'))
|
||||||
system_ss.add(when: 'CONFIG_IMX', if_true: files(
|
system_ss.add(when: 'CONFIG_IMX', if_true: files(
|
||||||
'imx25_ccm.c',
|
'imx25_ccm.c',
|
||||||
'imx31_ccm.c',
|
'imx31_ccm.c',
|
||||||
|
|
|
||||||
|
|
@ -12,6 +12,8 @@
|
||||||
#include "cpu.h"
|
#include "cpu.h"
|
||||||
#include "hw/char/imx_serial.h"
|
#include "hw/char/imx_serial.h"
|
||||||
#include "hw/intc/arm_gicv3_common.h"
|
#include "hw/intc/arm_gicv3_common.h"
|
||||||
|
#include "hw/misc/imx8mp_analog.h"
|
||||||
|
#include "hw/misc/imx8mp_ccm.h"
|
||||||
#include "qom/object.h"
|
#include "qom/object.h"
|
||||||
#include "qemu/units.h"
|
#include "qemu/units.h"
|
||||||
|
|
||||||
|
|
@ -32,6 +34,8 @@ struct FslImx8mpState {
|
||||||
|
|
||||||
ARMCPU cpu[FSL_IMX8MP_NUM_CPUS];
|
ARMCPU cpu[FSL_IMX8MP_NUM_CPUS];
|
||||||
GICv3State gic;
|
GICv3State gic;
|
||||||
|
IMX8MPCCMState ccm;
|
||||||
|
IMX8MPAnalogState analog;
|
||||||
IMXSerialState uart[FSL_IMX8MP_NUM_UARTS];
|
IMXSerialState uart[FSL_IMX8MP_NUM_UARTS];
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
81
include/hw/misc/imx8mp_analog.h
Normal file
81
include/hw/misc/imx8mp_analog.h
Normal file
|
|
@ -0,0 +1,81 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2025 Bernhard Beschow <shentey@gmail.com>
|
||||||
|
*
|
||||||
|
* i.MX8MP ANALOG IP block emulation code
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef IMX8MP_ANALOG_H
|
||||||
|
#define IMX8MP_ANALOG_H
|
||||||
|
|
||||||
|
#include "qom/object.h"
|
||||||
|
#include "hw/sysbus.h"
|
||||||
|
|
||||||
|
enum IMX8MPAnalogRegisters {
|
||||||
|
ANALOG_AUDIO_PLL1_GEN_CTRL = 0x000 / 4,
|
||||||
|
ANALOG_AUDIO_PLL1_FDIV_CTL0 = 0x004 / 4,
|
||||||
|
ANALOG_AUDIO_PLL1_FDIV_CTL1 = 0x008 / 4,
|
||||||
|
ANALOG_AUDIO_PLL1_SSCG_CTRL = 0x00c / 4,
|
||||||
|
ANALOG_AUDIO_PLL1_MNIT_CTRL = 0x010 / 4,
|
||||||
|
ANALOG_AUDIO_PLL2_GEN_CTRL = 0x014 / 4,
|
||||||
|
ANALOG_AUDIO_PLL2_FDIV_CTL0 = 0x018 / 4,
|
||||||
|
ANALOG_AUDIO_PLL2_FDIV_CTL1 = 0x01c / 4,
|
||||||
|
ANALOG_AUDIO_PLL2_SSCG_CTRL = 0x020 / 4,
|
||||||
|
ANALOG_AUDIO_PLL2_MNIT_CTRL = 0x024 / 4,
|
||||||
|
ANALOG_VIDEO_PLL1_GEN_CTRL = 0x028 / 4,
|
||||||
|
ANALOG_VIDEO_PLL1_FDIV_CTL0 = 0x02c / 4,
|
||||||
|
ANALOG_VIDEO_PLL1_FDIV_CTL1 = 0x030 / 4,
|
||||||
|
ANALOG_VIDEO_PLL1_SSCG_CTRL = 0x034 / 4,
|
||||||
|
ANALOG_VIDEO_PLL1_MNIT_CTRL = 0x038 / 4,
|
||||||
|
ANALOG_DRAM_PLL_GEN_CTRL = 0x050 / 4,
|
||||||
|
ANALOG_DRAM_PLL_FDIV_CTL0 = 0x054 / 4,
|
||||||
|
ANALOG_DRAM_PLL_FDIV_CTL1 = 0x058 / 4,
|
||||||
|
ANALOG_DRAM_PLL_SSCG_CTRL = 0x05c / 4,
|
||||||
|
ANALOG_DRAM_PLL_MNIT_CTRL = 0x060 / 4,
|
||||||
|
ANALOG_GPU_PLL_GEN_CTRL = 0x064 / 4,
|
||||||
|
ANALOG_GPU_PLL_FDIV_CTL0 = 0x068 / 4,
|
||||||
|
ANALOG_GPU_PLL_LOCKD_CTRL = 0x06c / 4,
|
||||||
|
ANALOG_GPU_PLL_MNIT_CTRL = 0x070 / 4,
|
||||||
|
ANALOG_VPU_PLL_GEN_CTRL = 0x074 / 4,
|
||||||
|
ANALOG_VPU_PLL_FDIV_CTL0 = 0x078 / 4,
|
||||||
|
ANALOG_VPU_PLL_LOCKD_CTRL = 0x07c / 4,
|
||||||
|
ANALOG_VPU_PLL_MNIT_CTRL = 0x080 / 4,
|
||||||
|
ANALOG_ARM_PLL_GEN_CTRL = 0x084 / 4,
|
||||||
|
ANALOG_ARM_PLL_FDIV_CTL0 = 0x088 / 4,
|
||||||
|
ANALOG_ARM_PLL_LOCKD_CTRL = 0x08c / 4,
|
||||||
|
ANALOG_ARM_PLL_MNIT_CTRL = 0x090 / 4,
|
||||||
|
ANALOG_SYS_PLL1_GEN_CTRL = 0x094 / 4,
|
||||||
|
ANALOG_SYS_PLL1_FDIV_CTL0 = 0x098 / 4,
|
||||||
|
ANALOG_SYS_PLL1_LOCKD_CTRL = 0x09c / 4,
|
||||||
|
ANALOG_SYS_PLL1_MNIT_CTRL = 0x100 / 4,
|
||||||
|
ANALOG_SYS_PLL2_GEN_CTRL = 0x104 / 4,
|
||||||
|
ANALOG_SYS_PLL2_FDIV_CTL0 = 0x108 / 4,
|
||||||
|
ANALOG_SYS_PLL2_LOCKD_CTRL = 0x10c / 4,
|
||||||
|
ANALOG_SYS_PLL2_MNIT_CTRL = 0x110 / 4,
|
||||||
|
ANALOG_SYS_PLL3_GEN_CTRL = 0x114 / 4,
|
||||||
|
ANALOG_SYS_PLL3_FDIV_CTL0 = 0x118 / 4,
|
||||||
|
ANALOG_SYS_PLL3_LOCKD_CTRL = 0x11c / 4,
|
||||||
|
ANALOG_SYS_PLL3_MNIT_CTRL = 0x120 / 4,
|
||||||
|
ANALOG_OSC_MISC_CFG = 0x124 / 4,
|
||||||
|
ANALOG_ANAMIX_PLL_MNIT_CTL = 0x128 / 4,
|
||||||
|
|
||||||
|
ANALOG_DIGPROG = 0x800 / 4,
|
||||||
|
ANALOG_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
#define TYPE_IMX8MP_ANALOG "imx8mp.analog"
|
||||||
|
OBJECT_DECLARE_SIMPLE_TYPE(IMX8MPAnalogState, IMX8MP_ANALOG)
|
||||||
|
|
||||||
|
struct IMX8MPAnalogState {
|
||||||
|
SysBusDevice parent_obj;
|
||||||
|
|
||||||
|
struct {
|
||||||
|
MemoryRegion container;
|
||||||
|
MemoryRegion analog;
|
||||||
|
} mmio;
|
||||||
|
|
||||||
|
uint32_t analog[ANALOG_MAX];
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* IMX8MP_ANALOG_H */
|
||||||
30
include/hw/misc/imx8mp_ccm.h
Normal file
30
include/hw/misc/imx8mp_ccm.h
Normal file
|
|
@ -0,0 +1,30 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2025 Bernhard Beschow <shentey@gmail.com>
|
||||||
|
*
|
||||||
|
* i.MX 8M Plus CCM IP block emulation code
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef IMX8MP_CCM_H
|
||||||
|
#define IMX8MP_CCM_H
|
||||||
|
|
||||||
|
#include "hw/misc/imx_ccm.h"
|
||||||
|
#include "qom/object.h"
|
||||||
|
|
||||||
|
enum IMX8MPCCMRegisters {
|
||||||
|
CCM_MAX = 0xc6fc / sizeof(uint32_t) + 1,
|
||||||
|
};
|
||||||
|
|
||||||
|
#define TYPE_IMX8MP_CCM "imx8mp.ccm"
|
||||||
|
OBJECT_DECLARE_SIMPLE_TYPE(IMX8MPCCMState, IMX8MP_CCM)
|
||||||
|
|
||||||
|
struct IMX8MPCCMState {
|
||||||
|
IMXCCMState parent_obj;
|
||||||
|
|
||||||
|
MemoryRegion iomem;
|
||||||
|
|
||||||
|
uint32_t ccm[CCM_MAX];
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* IMX8MP_CCM_H */
|
||||||
Loading…
Add table
Add a link
Reference in a new issue