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target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr

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We will require the context to handle RV64 word operations.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-5-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2021-08-23 12:55:09 -07:00 • committed by Alistair Francis
parent 4a083b563a
commit 867c81968a
9 changed files with 144 additions and 144 deletions
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4
target/riscv/insn_trans/trans_rvb.c.inc
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@ -424,7 +424,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
REQUIRE_EXT(ctx, RVB);
TCGv source1 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
gen_get_gpr(ctx, source1, a->rs1);
if (a->shamt < 32) {
tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
@ -432,7 +432,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
tcg_gen_shli_tl(source1, source1, a->shamt);
}
gen_set_gpr(a->rd, source1);
gen_set_gpr(ctx, a->rd, source1);
tcg_temp_free(source1);
return true;
}