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target/avr: Add instruction translation - Arithmetic and Logic Instructions

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This includes:
- ADD, ADC, ADIW
- SBIW, SUB, SUBI, SBC, SBCI
- AND, ANDI
- OR, ORI, EOR
- COM, NEG
- INC, DEC
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- DES

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-12-huth@tuxfamily.org>
[PMD: Added qemu_log_mask(LOG_UNIMP) in trans_DES()]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Michael Rolnik 2020-01-24 01:51:10 +01:00 • committed by Philippe Mathieu-Daudé
parent e03feba007
commit 865f3bb9e1
2 changed files with 896 additions and 0 deletions
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76
target/avr/insn.decode Normal file
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#
# AVR instruction decode definitions.
#
# Copyright (c) 2019-2020 Michael Rolnik <mrolnik@gmail.com>
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2.1 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
#
# regs_16_31_by_one = [16 .. 31]
# regs_16_23_by_one = [16 .. 23]
# regs_24_30_by_two = [24, 26, 28, 30]
# regs_00_30_by_two = [0, 2, 4, 6, 8, .. 30]
%rd 4:5
%rr 9:1 0:4
%rd_a 4:4 !function=to_regs_16_31_by_one
%rd_b 4:3 !function=to_regs_16_23_by_one
%rd_c 4:2 !function=to_regs_24_30_by_two
%rr_a 0:4 !function=to_regs_16_31_by_one
%rr_b 0:3 !function=to_regs_16_23_by_one
%imm6 6:2 0:4
%imm8 8:4 0:4
%io_imm 9:2 0:4
%ldst_d_imm 13:1 10:2 0:3
&rd_rr rd rr
&rd_imm rd imm
@op_rd_rr .... .. . ..... .... &rd_rr rd=%rd rr=%rr
@op_rd_imm6 .... .... .. .. .... &rd_imm rd=%rd_c imm=%imm6
@op_rd_imm8 .... .... .... .... &rd_imm rd=%rd_a imm=%imm8
@fmul .... .... . ... . ... &rd_rr rd=%rd_b rr=%rr_b
#
# Arithmetic Instructions
#
ADD 0000 11 . ..... .... @op_rd_rr
ADC 0001 11 . ..... .... @op_rd_rr
ADIW 1001 0110 .. .. .... @op_rd_imm6
SUB 0001 10 . ..... .... @op_rd_rr
SUBI 0101 .... .... .... @op_rd_imm8
SBC 0000 10 . ..... .... @op_rd_rr
SBCI 0100 .... .... .... @op_rd_imm8
SBIW 1001 0111 .. .. .... @op_rd_imm6
AND 0010 00 . ..... .... @op_rd_rr
ANDI 0111 .... .... .... @op_rd_imm8
OR 0010 10 . ..... .... @op_rd_rr
ORI 0110 .... .... .... @op_rd_imm8
EOR 0010 01 . ..... .... @op_rd_rr
COM 1001 010 rd:5 0000
NEG 1001 010 rd:5 0001
INC 1001 010 rd:5 0011
DEC 1001 010 rd:5 1010
MUL 1001 11 . ..... .... @op_rd_rr
MULS 0000 0010 .... .... &rd_rr rd=%rd_a rr=%rr_a
MULSU 0000 0011 0 ... 0 ... @fmul
FMUL 0000 0011 0 ... 1 ... @fmul
FMULS 0000 0011 1 ... 0 ... @fmul
FMULSU 0000 0011 1 ... 1 ... @fmul
DES 1001 0100 imm:4 1011