mirror of
https://github.com/Motorhead1991/qemu.git
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audio merge (malc)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1125 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
8f46820d92
commit
85571bc741
24 changed files with 6096 additions and 1732 deletions
309
hw/adlib.c
Normal file
309
hw/adlib.c
Normal file
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@ -0,0 +1,309 @@
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/*
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* QEMU Adlib emulation
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*
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* Copyright (c) 2004 Vassili Karpov (malc)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#define AUDIO_CAP "adlib"
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#include "audio/audio.h"
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#ifdef USE_YMF262
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#define HAS_YMF262 1
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#include "ymf262.h"
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void YMF262UpdateOneQEMU(int which, INT16 *dst, int length);
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#define SHIFT 2
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#else
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#include "fmopl.h"
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#define SHIFT 1
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#endif
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#ifdef _WIN32
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#include <windows.h>
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#define small_delay() Sleep (1)
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#else
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#define small_delay() usleep (1)
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#endif
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#define IO_READ_PROTO(name) \
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uint32_t name (void *opaque, uint32_t nport)
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#define IO_WRITE_PROTO(name) \
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void name (void *opaque, uint32_t nport, uint32_t val)
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static struct {
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int port;
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int freq;
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} conf = {0x220, 44100};
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typedef struct {
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int enabled;
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int active;
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int cparam;
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int64_t ticks;
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int bufpos;
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int16_t *mixbuf;
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double interval;
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QEMUTimer *ts, *opl_ts;
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SWVoice *voice;
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int left, pos, samples, bytes_per_second, old_free;
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int refcount;
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#ifndef USE_YMF262
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FM_OPL *opl;
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#endif
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} AdlibState;
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static AdlibState adlib;
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static IO_WRITE_PROTO(adlib_write)
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{
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AdlibState *s = opaque;
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int a = nport & 3;
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int status;
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s->ticks = qemu_get_clock (vm_clock);
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s->active = 1;
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AUD_enable (s->voice, 1);
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#ifdef USE_YMF262
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status = YMF262Write (0, a, val);
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#else
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status = OPLWrite (s->opl, a, val);
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#endif
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}
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static IO_READ_PROTO(adlib_read)
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{
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AdlibState *s = opaque;
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uint8_t data;
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int a = nport & 3;
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#ifdef USE_YMF262
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(void) s;
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data = YMF262Read (0, a);
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#else
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data = OPLRead (s->opl, a);
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#endif
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return data;
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}
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static void OPL_timer (void *opaque)
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{
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AdlibState *s = opaque;
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#ifdef USE_YMF262
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YMF262TimerOver (s->cparam >> 1, s->cparam & 1);
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#else
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OPLTimerOver (s->opl, s->cparam);
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#endif
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qemu_mod_timer (s->opl_ts, qemu_get_clock (vm_clock) + s->interval);
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}
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static void YMF262TimerHandler (int c, double interval_Sec)
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{
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AdlibState *s = &adlib;
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if (interval_Sec == 0.0) {
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qemu_del_timer (s->opl_ts);
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return;
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}
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s->cparam = c;
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s->interval = ticks_per_sec * interval_Sec;
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qemu_mod_timer (s->opl_ts, qemu_get_clock (vm_clock) + s->interval);
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small_delay ();
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}
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static int write_audio (AdlibState *s, int samples)
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{
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int net = 0;
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int ss = samples;
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while (samples) {
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int nbytes = samples << SHIFT;
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int wbytes = AUD_write (s->voice,
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s->mixbuf + (s->pos << (SHIFT - 1)),
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nbytes);
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int wsampl = wbytes >> SHIFT;
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samples -= wsampl;
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s->pos = (s->pos + wsampl) % s->samples;
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net += wsampl;
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if (!wbytes)
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break;
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}
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if (net > ss) {
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dolog ("WARNING: net > ss\n");
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}
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return net;
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}
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static void timer (void *opaque)
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{
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AdlibState *s = opaque;
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int elapsed, samples, net = 0;
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if (s->refcount)
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dolog ("refcount=%d\n", s->refcount);
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s->refcount += 1;
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if (!(s->active && s->enabled))
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goto reset;
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AUD_run ();
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while (s->left) {
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int written = write_audio (s, s->left);
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net += written;
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if (!written)
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goto reset2;
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s->left -= written;
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}
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s->pos = 0;
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elapsed = AUD_calc_elapsed (s->voice);
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if (!elapsed)
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goto reset2;
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/* elapsed = AUD_get_free (s->voice); */
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samples = elapsed >> SHIFT;
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if (!samples)
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goto reset2;
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samples = audio_MIN (samples, s->samples - s->pos);
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if (s->left)
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dolog ("left=%d samples=%d elapsed=%d free=%d\n",
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s->left, samples, elapsed, AUD_get_free (s->voice));
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if (!samples)
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goto reset2;
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#ifdef USE_YMF262
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YMF262UpdateOneQEMU (0, s->mixbuf + s->pos * 2, samples);
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#else
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YM3812UpdateOne (s->opl, s->mixbuf + s->pos, samples);
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#endif
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while (samples) {
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int written = write_audio (s, samples);
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net += written;
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if (!written)
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break;
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samples -= written;
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}
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if (!samples)
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s->pos = 0;
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s->left = samples;
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reset2:
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AUD_adjust (s->voice, net << SHIFT);
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reset:
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qemu_mod_timer (s->ts, qemu_get_clock (vm_clock) + ticks_per_sec / 1024);
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s->refcount -= 1;
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}
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static void Adlib_fini (AdlibState *s)
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{
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#ifdef USE_YMF262
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YMF262Shutdown ();
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#else
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if (s->opl) {
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OPLDestroy (s->opl);
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s->opl = NULL;
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}
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#endif
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if (s->opl_ts)
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qemu_free_timer (s->opl_ts);
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if (s->ts)
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qemu_free_timer (s->ts);
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#define maybe_free(p) if (p) qemu_free (p)
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maybe_free (s->mixbuf);
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#undef maybe_free
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s->active = 0;
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s->enabled = 0;
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}
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void Adlib_init (void)
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{
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AdlibState *s = &adlib;
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memset (s, 0, sizeof (*s));
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#ifdef USE_YMF262
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if (YMF262Init (1, 14318180, conf.freq)) {
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dolog ("YMF262Init %d failed\n", conf.freq);
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return;
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}
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else {
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YMF262SetTimerHandler (0, YMF262TimerHandler, 0);
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s->enabled = 1;
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}
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#else
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s->opl = OPLCreate (OPL_TYPE_YM3812, 3579545, conf.freq);
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if (!s->opl) {
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dolog ("OPLCreate %d failed\n", conf.freq);
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return;
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}
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else {
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OPLSetTimerHandler (s->opl, YMF262TimerHandler, 0);
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s->enabled = 1;
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}
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#endif
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s->opl_ts = qemu_new_timer (vm_clock, OPL_timer, s);
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if (!s->opl_ts) {
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dolog ("Can not get timer for adlib emulation\n");
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Adlib_fini (s);
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return;
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}
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s->ts = qemu_new_timer (vm_clock, timer, s);
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if (!s->opl_ts) {
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dolog ("Can not get timer for adlib emulation\n");
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Adlib_fini (s);
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return;
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}
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s->voice = AUD_open (s->voice, "adlib", conf.freq, SHIFT, AUD_FMT_S16);
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if (!s->voice) {
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Adlib_fini (s);
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return;
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}
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s->bytes_per_second = conf.freq << SHIFT;
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s->samples = AUD_get_buffer_size (s->voice) >> SHIFT;
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s->mixbuf = qemu_mallocz (s->samples << SHIFT);
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if (!s->mixbuf) {
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dolog ("not enough memory for adlib mixing buffer (%d)\n",
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s->samples << SHIFT);
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Adlib_fini (s);
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return;
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}
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register_ioport_read (0x388, 4, 1, adlib_read, s);
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register_ioport_write (0x388, 4, 1, adlib_write, s);
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register_ioport_read (conf.port, 4, 1, adlib_read, s);
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register_ioport_write (conf.port, 4, 1, adlib_write, s);
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register_ioport_read (conf.port + 8, 2, 1, adlib_read, s);
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register_ioport_write (conf.port + 8, 2, 1, adlib_write, s);
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qemu_mod_timer (s->ts, qemu_get_clock (vm_clock) + 1);
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}
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215
hw/dma.c
215
hw/dma.c
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@ -1,8 +1,8 @@
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/*
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* QEMU DMA emulation
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*
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* Copyright (c) 2003 Vassili Karpov (malc)
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*
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*
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* Copyright (c) 2003-2004 Vassili Karpov (malc)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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@ -23,9 +23,9 @@
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*/
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#include "vl.h"
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//#define DEBUG_DMA
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/* #define DEBUG_DMA */
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#define log(...) fprintf (stderr, "dma: " __VA_ARGS__)
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#define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
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#ifdef DEBUG_DMA
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#define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__)
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#define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
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@ -86,7 +86,7 @@ static void write_page (void *opaque, uint32_t nport, uint32_t data)
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ichan = channels[nport & 7];
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if (-1 == ichan) {
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log ("invalid channel %#x %#x\n", nport, data);
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dolog ("invalid channel %#x %#x\n", nport, data);
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return;
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}
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d->regs[ichan].page = data;
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@ -99,7 +99,7 @@ static void write_pageh (void *opaque, uint32_t nport, uint32_t data)
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ichan = channels[nport & 7];
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if (-1 == ichan) {
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log ("invalid channel %#x %#x\n", nport, data);
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dolog ("invalid channel %#x %#x\n", nport, data);
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return;
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}
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d->regs[ichan].pageh = data;
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@ -112,7 +112,7 @@ static uint32_t read_page (void *opaque, uint32_t nport)
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ichan = channels[nport & 7];
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if (-1 == ichan) {
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log ("invalid channel read %#x\n", nport);
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dolog ("invalid channel read %#x\n", nport);
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return 0;
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}
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return d->regs[ichan].page;
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@ -125,7 +125,7 @@ static uint32_t read_pageh (void *opaque, uint32_t nport)
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ichan = channels[nport & 7];
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if (-1 == ichan) {
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log ("invalid channel read %#x\n", nport);
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dolog ("invalid channel read %#x\n", nport);
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return 0;
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}
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return d->regs[ichan].pageh;
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@ -136,7 +136,7 @@ static inline void init_chan (struct dma_cont *d, int ichan)
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struct dma_regs *r;
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r = d->regs + ichan;
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r->now[ADDR] = r->base[0] << d->dshift;
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r->now[ADDR] = r->base[ADDR] << d->dshift;
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r->now[COUNT] = 0;
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}
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@ -152,7 +152,7 @@ static inline int getff (struct dma_cont *d)
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static uint32_t read_chan (void *opaque, uint32_t nport)
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{
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struct dma_cont *d = opaque;
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int ichan, nreg, iport, ff, val;
|
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int ichan, nreg, iport, ff, val, dir;
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struct dma_regs *r;
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iport = (nport >> d->dshift) & 0x0f;
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@ -160,12 +160,14 @@ static uint32_t read_chan (void *opaque, uint32_t nport)
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nreg = iport & 1;
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r = d->regs + ichan;
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dir = ((r->mode >> 5) & 1) ? -1 : 1;
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ff = getff (d);
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if (nreg)
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val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
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else
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val = r->now[ADDR] + r->now[COUNT];
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val = r->now[ADDR] + r->now[COUNT] * dir;
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|
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ldebug ("read_chan %#x -> %d\n", iport, val);
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return (val >> (d->dshift + (ff << 3))) & 0xff;
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}
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|
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@ -190,19 +192,19 @@ static void write_chan (void *opaque, uint32_t nport, uint32_t data)
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static void write_cont (void *opaque, uint32_t nport, uint32_t data)
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{
|
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struct dma_cont *d = opaque;
|
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int iport, ichan;
|
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int iport, ichan = 0;
|
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|
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iport = (nport >> d->dshift) & 0x0f;
|
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switch (iport) {
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case 8: /* command */
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case 0x08: /* command */
|
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if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
|
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log ("command %#x not supported\n", data);
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dolog ("command %#x not supported\n", data);
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return;
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}
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d->command = data;
|
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break;
|
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|
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case 9:
|
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case 0x09:
|
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ichan = data & 3;
|
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if (data & 4) {
|
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d->status |= 1 << (ichan + 4);
|
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|
|
@ -213,22 +215,19 @@ static void write_cont (void *opaque, uint32_t nport, uint32_t data)
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d->status &= ~(1 << ichan);
|
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break;
|
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|
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case 0xa: /* single mask */
|
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case 0x0a: /* single mask */
|
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if (data & 4)
|
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d->mask |= 1 << (data & 3);
|
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else
|
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d->mask &= ~(1 << (data & 3));
|
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break;
|
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|
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case 0xb: /* mode */
|
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case 0x0b: /* mode */
|
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{
|
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ichan = data & 3;
|
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#ifdef DEBUG_DMA
|
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int op;
|
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int ai;
|
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int dir;
|
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int opmode;
|
||||
|
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{
|
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int op, ai, dir, opmode;
|
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op = (data >> 2) & 3;
|
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ai = (data >> 4) & 1;
|
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dir = (data >> 5) & 1;
|
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|
|
@ -236,39 +235,39 @@ static void write_cont (void *opaque, uint32_t nport, uint32_t data)
|
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|
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linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
|
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ichan, op, ai, dir, opmode);
|
||||
}
|
||||
#endif
|
||||
|
||||
d->regs[ichan].mode = data;
|
||||
break;
|
||||
}
|
||||
|
||||
case 0xc: /* clear flip flop */
|
||||
case 0x0c: /* clear flip flop */
|
||||
d->flip_flop = 0;
|
||||
break;
|
||||
|
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case 0xd: /* reset */
|
||||
case 0x0d: /* reset */
|
||||
d->flip_flop = 0;
|
||||
d->mask = ~0;
|
||||
d->status = 0;
|
||||
d->command = 0;
|
||||
break;
|
||||
|
||||
case 0xe: /* clear mask for all channels */
|
||||
case 0x0e: /* clear mask for all channels */
|
||||
d->mask = 0;
|
||||
break;
|
||||
|
||||
case 0xf: /* write mask for all channels */
|
||||
case 0x0f: /* write mask for all channels */
|
||||
d->mask = data;
|
||||
break;
|
||||
|
||||
default:
|
||||
log ("dma: unknown iport %#x\n", iport);
|
||||
dolog ("unknown iport %#x\n", iport);
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef DEBUG_DMA
|
||||
if (0xc != iport) {
|
||||
linfo ("nport %#06x, ichan % 2d, val %#06x\n",
|
||||
linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
|
||||
nport, ichan, data);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -278,20 +277,22 @@ static uint32_t read_cont (void *opaque, uint32_t nport)
|
|||
{
|
||||
struct dma_cont *d = opaque;
|
||||
int iport, val;
|
||||
|
||||
|
||||
iport = (nport >> d->dshift) & 0x0f;
|
||||
switch (iport) {
|
||||
case 0x08: /* status */
|
||||
case 0x08: /* status */
|
||||
val = d->status;
|
||||
d->status &= 0xf0;
|
||||
break;
|
||||
case 0x0f: /* mask */
|
||||
case 0x0f: /* mask */
|
||||
val = d->mask;
|
||||
break;
|
||||
default:
|
||||
val = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
|
||||
return val;
|
||||
}
|
||||
|
||||
|
|
@ -322,23 +323,27 @@ void DMA_release_DREQ (int nchan)
|
|||
|
||||
static void channel_run (int ncont, int ichan)
|
||||
{
|
||||
struct dma_regs *r;
|
||||
int n;
|
||||
target_ulong addr;
|
||||
/* int ai, dir; */
|
||||
struct dma_regs *r = &dma_controllers[ncont].regs[ichan];
|
||||
#ifdef DEBUG_DMA
|
||||
int dir, opmode;
|
||||
|
||||
dir = (r->mode >> 5) & 1;
|
||||
opmode = (r->mode >> 6) & 3;
|
||||
|
||||
if (dir) {
|
||||
dolog ("DMA in address decrement mode\n");
|
||||
}
|
||||
if (opmode != 1) {
|
||||
dolog ("DMA not in single mode select %#x\n", opmode);
|
||||
}
|
||||
#endif
|
||||
|
||||
r = dma_controllers[ncont].regs + ichan;
|
||||
/* ai = r->mode & 16; */
|
||||
/* dir = r->mode & 32 ? -1 : 1; */
|
||||
|
||||
/* NOTE: pageh is only used by PPC PREP */
|
||||
addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
|
||||
n = r->transfer_handler (r->opaque, addr,
|
||||
(r->base[COUNT] << ncont) + (1 << ncont));
|
||||
n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
|
||||
r->now[COUNT], (r->base[COUNT] + 1) << ncont);
|
||||
r->now[COUNT] = n;
|
||||
|
||||
ldebug ("dma_pos %d size %d\n",
|
||||
n, (r->base[1] << ncont) + (1 << ncont));
|
||||
ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);
|
||||
}
|
||||
|
||||
void DMA_run (void)
|
||||
|
|
@ -361,7 +366,7 @@ void DMA_run (void)
|
|||
}
|
||||
|
||||
void DMA_register_channel (int nchan,
|
||||
DMA_transfer_handler transfer_handler,
|
||||
DMA_transfer_handler transfer_handler,
|
||||
void *opaque)
|
||||
{
|
||||
struct dma_regs *r;
|
||||
|
|
@ -375,6 +380,50 @@ void DMA_register_channel (int nchan,
|
|||
r->opaque = opaque;
|
||||
}
|
||||
|
||||
int DMA_read_memory (int nchan, void *buf, int pos, int len)
|
||||
{
|
||||
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
|
||||
target_ulong addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
|
||||
|
||||
if (r->mode & 0x20) {
|
||||
int i;
|
||||
uint8_t *p = buf;
|
||||
|
||||
cpu_physical_memory_read (addr - pos - len, buf, len);
|
||||
/* What about 16bit transfers? */
|
||||
for (i = 0; i < len >> 1; i++) {
|
||||
uint8_t b = p[len - i - 1];
|
||||
p[i] = b;
|
||||
}
|
||||
}
|
||||
else
|
||||
cpu_physical_memory_read (addr + pos, buf, len);
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
int DMA_write_memory (int nchan, void *buf, int pos, int len)
|
||||
{
|
||||
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
|
||||
target_ulong addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
|
||||
|
||||
if (r->mode & 0x20) {
|
||||
int i;
|
||||
uint8_t *p = buf;
|
||||
|
||||
cpu_physical_memory_write (addr - pos - len, buf, len);
|
||||
/* What about 16bit transfers? */
|
||||
for (i = 0; i < len; i++) {
|
||||
uint8_t b = p[len - i - 1];
|
||||
p[i] = b;
|
||||
}
|
||||
}
|
||||
else
|
||||
cpu_physical_memory_write (addr + pos, buf, len);
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
/* request the emulator to transfer a new DMA memory block ASAP */
|
||||
void DMA_schedule(int nchan)
|
||||
{
|
||||
|
|
@ -388,7 +437,7 @@ static void dma_reset(void *opaque)
|
|||
}
|
||||
|
||||
/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
|
||||
static void dma_init2(struct dma_cont *d, int base, int dshift,
|
||||
static void dma_init2(struct dma_cont *d, int base, int dshift,
|
||||
int page_base, int pageh_base)
|
||||
{
|
||||
const static int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
|
||||
|
|
@ -400,31 +449,87 @@ static void dma_init2(struct dma_cont *d, int base, int dshift,
|
|||
register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);
|
||||
}
|
||||
for (i = 0; i < LENOFA (page_port_list); i++) {
|
||||
register_ioport_write (page_base + page_port_list[i], 1, 1,
|
||||
register_ioport_write (page_base + page_port_list[i], 1, 1,
|
||||
write_page, d);
|
||||
register_ioport_read (page_base + page_port_list[i], 1, 1,
|
||||
register_ioport_read (page_base + page_port_list[i], 1, 1,
|
||||
read_page, d);
|
||||
if (pageh_base >= 0) {
|
||||
register_ioport_write (pageh_base + page_port_list[i], 1, 1,
|
||||
register_ioport_write (pageh_base + page_port_list[i], 1, 1,
|
||||
write_pageh, d);
|
||||
register_ioport_read (pageh_base + page_port_list[i], 1, 1,
|
||||
register_ioport_read (pageh_base + page_port_list[i], 1, 1,
|
||||
read_pageh, d);
|
||||
}
|
||||
}
|
||||
for (i = 0; i < 8; i++) {
|
||||
register_ioport_write (base + ((i + 8) << dshift), 1, 1,
|
||||
register_ioport_write (base + ((i + 8) << dshift), 1, 1,
|
||||
write_cont, d);
|
||||
register_ioport_read (base + ((i + 8) << dshift), 1, 1,
|
||||
register_ioport_read (base + ((i + 8) << dshift), 1, 1,
|
||||
read_cont, d);
|
||||
}
|
||||
qemu_register_reset(dma_reset, d);
|
||||
dma_reset(d);
|
||||
}
|
||||
|
||||
static void dma_save (QEMUFile *f, void *opaque)
|
||||
{
|
||||
struct dma_cont *d = opaque;
|
||||
int i;
|
||||
|
||||
/* qemu_put_8s (f, &d->status); */
|
||||
qemu_put_8s (f, &d->command);
|
||||
qemu_put_8s (f, &d->mask);
|
||||
qemu_put_8s (f, &d->flip_flop);
|
||||
qemu_put_be32s (f, &d->dshift);
|
||||
|
||||
for (i = 0; i < 4; ++i) {
|
||||
struct dma_regs *r = &d->regs[i];
|
||||
qemu_put_be32s (f, &r->now[0]);
|
||||
qemu_put_be32s (f, &r->now[1]);
|
||||
qemu_put_be16s (f, &r->base[0]);
|
||||
qemu_put_be16s (f, &r->base[1]);
|
||||
qemu_put_8s (f, &r->mode);
|
||||
qemu_put_8s (f, &r->page);
|
||||
qemu_put_8s (f, &r->pageh);
|
||||
qemu_put_8s (f, &r->dack);
|
||||
qemu_put_8s (f, &r->eop);
|
||||
}
|
||||
}
|
||||
|
||||
static int dma_load (QEMUFile *f, void *opaque, int version_id)
|
||||
{
|
||||
struct dma_cont *d = opaque;
|
||||
int i;
|
||||
|
||||
if (version_id != 1)
|
||||
return -EINVAL;
|
||||
|
||||
/* qemu_get_8s (f, &d->status); */
|
||||
qemu_get_8s (f, &d->command);
|
||||
qemu_get_8s (f, &d->mask);
|
||||
qemu_get_8s (f, &d->flip_flop);
|
||||
qemu_get_be32s (f, &d->dshift);
|
||||
|
||||
for (i = 0; i < 4; ++i) {
|
||||
struct dma_regs *r = &d->regs[i];
|
||||
qemu_get_be32s (f, &r->now[0]);
|
||||
qemu_get_be32s (f, &r->now[1]);
|
||||
qemu_get_be16s (f, &r->base[0]);
|
||||
qemu_get_be16s (f, &r->base[1]);
|
||||
qemu_get_8s (f, &r->mode);
|
||||
qemu_get_8s (f, &r->page);
|
||||
qemu_get_8s (f, &r->pageh);
|
||||
qemu_get_8s (f, &r->dack);
|
||||
qemu_get_8s (f, &r->eop);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void DMA_init (int high_page_enable)
|
||||
{
|
||||
dma_init2(&dma_controllers[0], 0x00, 0, 0x80,
|
||||
dma_init2(&dma_controllers[0], 0x00, 0, 0x80,
|
||||
high_page_enable ? 0x480 : -1);
|
||||
dma_init2(&dma_controllers[1], 0xc0, 1, 0x88,
|
||||
high_page_enable ? 0x488 : -1);
|
||||
register_savevm ("dma", 0, 1, dma_save, dma_load, &dma_controllers[0]);
|
||||
register_savevm ("dma", 1, 1, dma_save, dma_load, &dma_controllers[1]);
|
||||
}
|
||||
|
|
|
|||
31
hw/fdc.c
31
hw/fdc.c
|
|
@ -313,7 +313,8 @@ static void fd_reset (fdrive_t *drv)
|
|||
|
||||
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
|
||||
static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
|
||||
static int fdctrl_transfer_handler (void *opaque, target_ulong addr, int size);
|
||||
static int fdctrl_transfer_handler (void *opaque, int nchan,
|
||||
int dma_pos, int dma_len);
|
||||
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status);
|
||||
static void fdctrl_result_timer(void *opaque);
|
||||
|
||||
|
|
@ -908,7 +909,8 @@ static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
|
|||
}
|
||||
|
||||
/* handlers for DMA transfers */
|
||||
static int fdctrl_transfer_handler (void *opaque, target_ulong addr, int size)
|
||||
static int fdctrl_transfer_handler (void *opaque, int nchan,
|
||||
int dma_pos, int dma_len)
|
||||
{
|
||||
fdctrl_t *fdctrl;
|
||||
fdrive_t *cur_drv;
|
||||
|
|
@ -924,8 +926,8 @@ static int fdctrl_transfer_handler (void *opaque, target_ulong addr, int size)
|
|||
if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
|
||||
fdctrl->data_dir == FD_DIR_SCANH)
|
||||
status2 = 0x04;
|
||||
if (size > fdctrl->data_len)
|
||||
size = fdctrl->data_len;
|
||||
if (dma_len > fdctrl->data_len)
|
||||
dma_len = fdctrl->data_len;
|
||||
if (cur_drv->bs == NULL) {
|
||||
if (fdctrl->data_dir == FD_DIR_WRITE)
|
||||
fdctrl_stop_transfer(fdctrl, 0x60, 0x00, 0x00);
|
||||
|
|
@ -935,8 +937,8 @@ static int fdctrl_transfer_handler (void *opaque, target_ulong addr, int size)
|
|||
goto transfer_error;
|
||||
}
|
||||
rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
|
||||
for (start_pos = fdctrl->data_pos; fdctrl->data_pos < size;) {
|
||||
len = size - fdctrl->data_pos;
|
||||
for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
|
||||
len = dma_len - fdctrl->data_pos;
|
||||
if (len + rel_pos > FD_SECTOR_LEN)
|
||||
len = FD_SECTOR_LEN - rel_pos;
|
||||
FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x %02x "
|
||||
|
|
@ -958,13 +960,17 @@ static int fdctrl_transfer_handler (void *opaque, target_ulong addr, int size)
|
|||
switch (fdctrl->data_dir) {
|
||||
case FD_DIR_READ:
|
||||
/* READ commands */
|
||||
cpu_physical_memory_write(addr + fdctrl->data_pos,
|
||||
fdctrl->fifo + rel_pos, len);
|
||||
DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
|
||||
fdctrl->data_pos, len);
|
||||
/* cpu_physical_memory_write(addr + fdctrl->data_pos, */
|
||||
/* fdctrl->fifo + rel_pos, len); */
|
||||
break;
|
||||
case FD_DIR_WRITE:
|
||||
/* WRITE commands */
|
||||
cpu_physical_memory_read(addr + fdctrl->data_pos,
|
||||
fdctrl->fifo + rel_pos, len);
|
||||
DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
|
||||
fdctrl->data_pos, len);
|
||||
/* cpu_physical_memory_read(addr + fdctrl->data_pos, */
|
||||
/* fdctrl->fifo + rel_pos, len); */
|
||||
if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
|
||||
fdctrl->fifo, 1) < 0) {
|
||||
FLOPPY_ERROR("writting sector %d\n", fd_sector(cur_drv));
|
||||
|
|
@ -977,8 +983,9 @@ static int fdctrl_transfer_handler (void *opaque, target_ulong addr, int size)
|
|||
{
|
||||
uint8_t tmpbuf[FD_SECTOR_LEN];
|
||||
int ret;
|
||||
cpu_physical_memory_read(addr + fdctrl->data_pos,
|
||||
tmpbuf, len);
|
||||
DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
|
||||
/* cpu_physical_memory_read(addr + fdctrl->data_pos, */
|
||||
/* tmpbuf, len); */
|
||||
ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
|
||||
if (ret == 0) {
|
||||
status2 = 0x08;
|
||||
|
|
|
|||
1390
hw/fmopl.c
Normal file
1390
hw/fmopl.c
Normal file
File diff suppressed because it is too large
Load diff
174
hw/fmopl.h
Normal file
174
hw/fmopl.h
Normal file
|
|
@ -0,0 +1,174 @@
|
|||
#ifndef __FMOPL_H_
|
||||
#define __FMOPL_H_
|
||||
|
||||
/* --- select emulation chips --- */
|
||||
#define BUILD_YM3812 (HAS_YM3812)
|
||||
//#define BUILD_YM3526 (HAS_YM3526)
|
||||
//#define BUILD_Y8950 (HAS_Y8950)
|
||||
|
||||
/* --- system optimize --- */
|
||||
/* select bit size of output : 8 or 16 */
|
||||
#define OPL_OUTPUT_BIT 16
|
||||
|
||||
/* compiler dependence */
|
||||
#ifndef OSD_CPU_H
|
||||
#define OSD_CPU_H
|
||||
typedef unsigned char UINT8; /* unsigned 8bit */
|
||||
typedef unsigned short UINT16; /* unsigned 16bit */
|
||||
typedef unsigned int UINT32; /* unsigned 32bit */
|
||||
typedef signed char INT8; /* signed 8bit */
|
||||
typedef signed short INT16; /* signed 16bit */
|
||||
typedef signed int INT32; /* signed 32bit */
|
||||
#endif
|
||||
|
||||
#if (OPL_OUTPUT_BIT==16)
|
||||
typedef INT16 OPLSAMPLE;
|
||||
#endif
|
||||
#if (OPL_OUTPUT_BIT==8)
|
||||
typedef unsigned char OPLSAMPLE;
|
||||
#endif
|
||||
|
||||
|
||||
#if BUILD_Y8950
|
||||
#include "ymdeltat.h"
|
||||
#endif
|
||||
|
||||
typedef void (*OPL_TIMERHANDLER)(int channel,double interval_Sec);
|
||||
typedef void (*OPL_IRQHANDLER)(int param,int irq);
|
||||
typedef void (*OPL_UPDATEHANDLER)(int param,int min_interval_us);
|
||||
typedef void (*OPL_PORTHANDLER_W)(int param,unsigned char data);
|
||||
typedef unsigned char (*OPL_PORTHANDLER_R)(int param);
|
||||
|
||||
/* !!!!! here is private section , do not access there member direct !!!!! */
|
||||
|
||||
#define OPL_TYPE_WAVESEL 0x01 /* waveform select */
|
||||
#define OPL_TYPE_ADPCM 0x02 /* DELTA-T ADPCM unit */
|
||||
#define OPL_TYPE_KEYBOARD 0x04 /* keyboard interface */
|
||||
#define OPL_TYPE_IO 0x08 /* I/O port */
|
||||
|
||||
/* Saving is necessary for member of the 'R' mark for suspend/resume */
|
||||
/* ---------- OPL one of slot ---------- */
|
||||
typedef struct fm_opl_slot {
|
||||
INT32 TL; /* total level :TL << 8 */
|
||||
INT32 TLL; /* adjusted now TL */
|
||||
UINT8 KSR; /* key scale rate :(shift down bit) */
|
||||
INT32 *AR; /* attack rate :&AR_TABLE[AR<<2] */
|
||||
INT32 *DR; /* decay rate :&DR_TALBE[DR<<2] */
|
||||
INT32 SL; /* sustin level :SL_TALBE[SL] */
|
||||
INT32 *RR; /* release rate :&DR_TABLE[RR<<2] */
|
||||
UINT8 ksl; /* keyscale level :(shift down bits) */
|
||||
UINT8 ksr; /* key scale rate :kcode>>KSR */
|
||||
UINT32 mul; /* multiple :ML_TABLE[ML] */
|
||||
UINT32 Cnt; /* frequency count : */
|
||||
UINT32 Incr; /* frequency step : */
|
||||
/* envelope generator state */
|
||||
UINT8 eg_typ; /* envelope type flag */
|
||||
UINT8 evm; /* envelope phase */
|
||||
INT32 evc; /* envelope counter */
|
||||
INT32 eve; /* envelope counter end point */
|
||||
INT32 evs; /* envelope counter step */
|
||||
INT32 evsa; /* envelope step for AR :AR[ksr] */
|
||||
INT32 evsd; /* envelope step for DR :DR[ksr] */
|
||||
INT32 evsr; /* envelope step for RR :RR[ksr] */
|
||||
/* LFO */
|
||||
UINT8 ams; /* ams flag */
|
||||
UINT8 vib; /* vibrate flag */
|
||||
/* wave selector */
|
||||
INT32 **wavetable;
|
||||
}OPL_SLOT;
|
||||
|
||||
/* ---------- OPL one of channel ---------- */
|
||||
typedef struct fm_opl_channel {
|
||||
OPL_SLOT SLOT[2];
|
||||
UINT8 CON; /* connection type */
|
||||
UINT8 FB; /* feed back :(shift down bit) */
|
||||
INT32 *connect1; /* slot1 output pointer */
|
||||
INT32 *connect2; /* slot2 output pointer */
|
||||
INT32 op1_out[2]; /* slot1 output for selfeedback */
|
||||
/* phase generator state */
|
||||
UINT32 block_fnum; /* block+fnum : */
|
||||
UINT8 kcode; /* key code : KeyScaleCode */
|
||||
UINT32 fc; /* Freq. Increment base */
|
||||
UINT32 ksl_base; /* KeyScaleLevel Base step */
|
||||
UINT8 keyon; /* key on/off flag */
|
||||
} OPL_CH;
|
||||
|
||||
/* OPL state */
|
||||
typedef struct fm_opl_f {
|
||||
UINT8 type; /* chip type */
|
||||
int clock; /* master clock (Hz) */
|
||||
int rate; /* sampling rate (Hz) */
|
||||
double freqbase; /* frequency base */
|
||||
double TimerBase; /* Timer base time (==sampling time) */
|
||||
UINT8 address; /* address register */
|
||||
UINT8 status; /* status flag */
|
||||
UINT8 statusmask; /* status mask */
|
||||
UINT32 mode; /* Reg.08 : CSM , notesel,etc. */
|
||||
/* Timer */
|
||||
int T[2]; /* timer counter */
|
||||
UINT8 st[2]; /* timer enable */
|
||||
/* FM channel slots */
|
||||
OPL_CH *P_CH; /* pointer of CH */
|
||||
int max_ch; /* maximum channel */
|
||||
/* Rythm sention */
|
||||
UINT8 rythm; /* Rythm mode , key flag */
|
||||
#if BUILD_Y8950
|
||||
/* Delta-T ADPCM unit (Y8950) */
|
||||
YM_DELTAT *deltat; /* DELTA-T ADPCM */
|
||||
#endif
|
||||
/* Keyboard / I/O interface unit (Y8950) */
|
||||
UINT8 portDirection;
|
||||
UINT8 portLatch;
|
||||
OPL_PORTHANDLER_R porthandler_r;
|
||||
OPL_PORTHANDLER_W porthandler_w;
|
||||
int port_param;
|
||||
OPL_PORTHANDLER_R keyboardhandler_r;
|
||||
OPL_PORTHANDLER_W keyboardhandler_w;
|
||||
int keyboard_param;
|
||||
/* time tables */
|
||||
INT32 AR_TABLE[75]; /* atttack rate tables */
|
||||
INT32 DR_TABLE[75]; /* decay rate tables */
|
||||
UINT32 FN_TABLE[1024]; /* fnumber -> increment counter */
|
||||
/* LFO */
|
||||
INT32 *ams_table;
|
||||
INT32 *vib_table;
|
||||
INT32 amsCnt;
|
||||
INT32 amsIncr;
|
||||
INT32 vibCnt;
|
||||
INT32 vibIncr;
|
||||
/* wave selector enable flag */
|
||||
UINT8 wavesel;
|
||||
/* external event callback handler */
|
||||
OPL_TIMERHANDLER TimerHandler; /* TIMER handler */
|
||||
int TimerParam; /* TIMER parameter */
|
||||
OPL_IRQHANDLER IRQHandler; /* IRQ handler */
|
||||
int IRQParam; /* IRQ parameter */
|
||||
OPL_UPDATEHANDLER UpdateHandler; /* stream update handler */
|
||||
int UpdateParam; /* stream update parameter */
|
||||
} FM_OPL;
|
||||
|
||||
/* ---------- Generic interface section ---------- */
|
||||
#define OPL_TYPE_YM3526 (0)
|
||||
#define OPL_TYPE_YM3812 (OPL_TYPE_WAVESEL)
|
||||
#define OPL_TYPE_Y8950 (OPL_TYPE_ADPCM|OPL_TYPE_KEYBOARD|OPL_TYPE_IO)
|
||||
|
||||
FM_OPL *OPLCreate(int type, int clock, int rate);
|
||||
void OPLDestroy(FM_OPL *OPL);
|
||||
void OPLSetTimerHandler(FM_OPL *OPL,OPL_TIMERHANDLER TimerHandler,int channelOffset);
|
||||
void OPLSetIRQHandler(FM_OPL *OPL,OPL_IRQHANDLER IRQHandler,int param);
|
||||
void OPLSetUpdateHandler(FM_OPL *OPL,OPL_UPDATEHANDLER UpdateHandler,int param);
|
||||
/* Y8950 port handlers */
|
||||
void OPLSetPortHandler(FM_OPL *OPL,OPL_PORTHANDLER_W PortHandler_w,OPL_PORTHANDLER_R PortHandler_r,int param);
|
||||
void OPLSetKeyboardHandler(FM_OPL *OPL,OPL_PORTHANDLER_W KeyboardHandler_w,OPL_PORTHANDLER_R KeyboardHandler_r,int param);
|
||||
|
||||
void OPLResetChip(FM_OPL *OPL);
|
||||
int OPLWrite(FM_OPL *OPL,int a,int v);
|
||||
unsigned char OPLRead(FM_OPL *OPL,int a);
|
||||
int OPLTimerOver(FM_OPL *OPL,int c);
|
||||
|
||||
/* YM3626/YM3812 local section */
|
||||
void YM3812UpdateOne(FM_OPL *OPL, INT16 *buffer, int length);
|
||||
|
||||
void Y8950UpdateOne(FM_OPL *OPL, INT16 *buffer, int length);
|
||||
|
||||
#endif
|
||||
3
hw/pc.c
3
hw/pc.c
|
|
@ -554,13 +554,10 @@ void pc_init(int ram_size, int vga_ram_size, int boot_device,
|
|||
kbd_init();
|
||||
DMA_init(0);
|
||||
|
||||
#ifndef _WIN32
|
||||
if (audio_enabled) {
|
||||
/* no audio supported yet for win32 */
|
||||
AUD_init();
|
||||
SB16_init();
|
||||
}
|
||||
#endif
|
||||
|
||||
floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue