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target/ppc: implement vsraq

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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-23-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Matheus Ferst 2022-03-02 06:51:37 +01:00 • committed by Cédric Le Goater
parent 946c3491c6
commit 85085bbc63
2 changed files with 18 additions and 6 deletions
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1
target/ppc/insn32.decode
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@ -485,6 +485,7 @@ VSRAB 000100 ..... ..... ..... 01100000100 @VX
VSRAH 000100 ..... ..... ..... 01101000100 @VX VSRAH 000100 ..... ..... ..... 01101000100 @VX
VSRAW 000100 ..... ..... ..... 01110000100 @VX VSRAW 000100 ..... ..... ..... 01110000100 @VX
VSRAD 000100 ..... ..... ..... 01111000100 @VX VSRAD 000100 ..... ..... ..... 01111000100 @VX
VSRAQ 000100 ..... ..... ..... 01100000101 @VX
## Vector Integer Arithmetic Instructions ## Vector Integer Arithmetic Instructions

23
target/ppc/translate/vmx-impl.c.inc
View file

@ -834,9 +834,10 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv); TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv); TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right) static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right,
bool alg)
{ {
TCGv_i64 hi, lo, t0, n, zero = tcg_constant_i64(0); TCGv_i64 hi, lo, t0, t1, n, zero = tcg_constant_i64(0);
REQUIRE_VECTOR(ctx); REQUIRE_VECTOR(ctx);
@ -844,6 +845,7 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right)
hi = tcg_temp_new_i64(); hi = tcg_temp_new_i64();
lo = tcg_temp_new_i64(); lo = tcg_temp_new_i64();
t0 = tcg_temp_new_i64(); t0 = tcg_temp_new_i64();
t1 = tcg_const_i64(0);
get_avr64(lo, a->vra, false); get_avr64(lo, a->vra, false);
get_avr64(hi, a->vra, true); get_avr64(hi, a->vra, true);
@ -853,7 +855,10 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right)
tcg_gen_andi_i64(t0, n, 64); tcg_gen_andi_i64(t0, n, 64);
if (right) { if (right) {
tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, hi, lo); tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, hi, lo);
tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, zero, hi); if (alg) {
tcg_gen_sari_i64(t1, lo, 63);
}
tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, t1, hi);
} else { } else {
tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi); tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi);
tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo); tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo);
@ -861,7 +866,11 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right)
tcg_gen_andi_i64(n, n, 0x3F); tcg_gen_andi_i64(n, n, 0x3F);
if (right) { if (right) {
tcg_gen_shr_i64(t0, hi, n); if (alg) {
tcg_gen_sar_i64(t0, hi, n);
} else {
tcg_gen_shr_i64(t0, hi, n);
}
} else { } else {
tcg_gen_shl_i64(t0, lo, n); tcg_gen_shl_i64(t0, lo, n);
} }
@ -886,13 +895,15 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right)
tcg_temp_free_i64(hi); tcg_temp_free_i64(hi);
tcg_temp_free_i64(lo); tcg_temp_free_i64(lo);
tcg_temp_free_i64(t0); tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(n); tcg_temp_free_i64(n);
return true; return true;
} }
TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false); TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false, false);
TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true); TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true, false);
TRANS_FLAGS2(ISA310, VSRAQ, do_vector_shift_quad, true, true);
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \ #define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \ static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \