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hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng
Alistair Francis
parent
406fafd5d0
commit
84fcf3c151
10 changed files with 14 additions and 6 deletions
524
hw/intc/sifive_plic.c
Normal file
524
hw/intc/sifive_plic.c
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@ -0,0 +1,524 @@
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/*
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* SiFive PLIC (Platform Level Interrupt Controller)
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This provides a parameterizable interrupt controller based on SiFive's PLIC.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/error-report.h"
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#include "hw/sysbus.h"
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#include "hw/pci/msi.h"
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#include "hw/boards.h"
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#include "hw/qdev-properties.h"
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#include "hw/intc/sifive_plic.h"
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#include "target/riscv/cpu.h"
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#include "sysemu/sysemu.h"
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#define RISCV_DEBUG_PLIC 0
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static PLICMode char_to_mode(char c)
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{
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switch (c) {
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case 'U': return PLICMode_U;
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case 'S': return PLICMode_S;
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case 'H': return PLICMode_H;
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case 'M': return PLICMode_M;
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default:
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error_report("plic: invalid mode '%c'", c);
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exit(1);
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}
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}
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static char mode_to_char(PLICMode m)
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{
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switch (m) {
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case PLICMode_U: return 'U';
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case PLICMode_S: return 'S';
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case PLICMode_H: return 'H';
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case PLICMode_M: return 'M';
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default: return '?';
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}
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}
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static void sifive_plic_print_state(SiFivePLICState *plic)
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{
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int i;
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int addrid;
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/* pending */
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qemu_log("pending : ");
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for (i = plic->bitfield_words - 1; i >= 0; i--) {
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qemu_log("%08x", plic->pending[i]);
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}
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qemu_log("\n");
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/* pending */
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qemu_log("claimed : ");
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for (i = plic->bitfield_words - 1; i >= 0; i--) {
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qemu_log("%08x", plic->claimed[i]);
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}
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qemu_log("\n");
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for (addrid = 0; addrid < plic->num_addrs; addrid++) {
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qemu_log("hart%d-%c enable: ",
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plic->addr_config[addrid].hartid,
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mode_to_char(plic->addr_config[addrid].mode));
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for (i = plic->bitfield_words - 1; i >= 0; i--) {
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qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + i]);
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}
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qemu_log("\n");
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}
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}
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static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
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{
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uint32_t old, new, cmp = atomic_read(a);
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do {
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old = cmp;
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new = (old & ~mask) | (value & mask);
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cmp = atomic_cmpxchg(a, old, new);
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} while (old != cmp);
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return old;
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}
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static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level)
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{
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atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level);
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}
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static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
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{
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atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
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}
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static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid)
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{
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int i, j;
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for (i = 0; i < plic->bitfield_words; i++) {
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uint32_t pending_enabled_not_claimed =
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(plic->pending[i] & ~plic->claimed[i]) &
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plic->enable[addrid * plic->bitfield_words + i];
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if (!pending_enabled_not_claimed) {
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continue;
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}
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for (j = 0; j < 32; j++) {
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int irq = (i << 5) + j;
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uint32_t prio = plic->source_priority[irq];
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int enabled = pending_enabled_not_claimed & (1 << j);
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if (enabled && prio > plic->target_priority[addrid]) {
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return 1;
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}
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}
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}
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return 0;
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}
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static void sifive_plic_update(SiFivePLICState *plic)
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{
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int addrid;
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/* raise irq on harts where this irq is enabled */
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for (addrid = 0; addrid < plic->num_addrs; addrid++) {
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uint32_t hartid = plic->addr_config[addrid].hartid;
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PLICMode mode = plic->addr_config[addrid].mode;
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CPUState *cpu = qemu_get_cpu(hartid);
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CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
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if (!env) {
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continue;
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}
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int level = sifive_plic_irqs_pending(plic, addrid);
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switch (mode) {
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case PLICMode_M:
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riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
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break;
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case PLICMode_S:
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riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
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break;
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default:
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break;
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}
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}
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if (RISCV_DEBUG_PLIC) {
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sifive_plic_print_state(plic);
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}
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}
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static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
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{
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int i, j;
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uint32_t max_irq = 0;
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uint32_t max_prio = plic->target_priority[addrid];
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for (i = 0; i < plic->bitfield_words; i++) {
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uint32_t pending_enabled_not_claimed =
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(plic->pending[i] & ~plic->claimed[i]) &
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plic->enable[addrid * plic->bitfield_words + i];
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if (!pending_enabled_not_claimed) {
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continue;
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}
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for (j = 0; j < 32; j++) {
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int irq = (i << 5) + j;
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uint32_t prio = plic->source_priority[irq];
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int enabled = pending_enabled_not_claimed & (1 << j);
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if (enabled && prio > max_prio) {
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max_irq = irq;
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max_prio = prio;
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}
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}
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}
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if (max_irq) {
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sifive_plic_set_pending(plic, max_irq, false);
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sifive_plic_set_claimed(plic, max_irq, true);
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}
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return max_irq;
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}
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static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
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{
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SiFivePLICState *plic = opaque;
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/* writes must be 4 byte words */
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if ((addr & 0x3) != 0) {
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goto err;
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}
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if (addr >= plic->priority_base && /* 4 bytes per source */
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addr < plic->priority_base + (plic->num_sources << 2))
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{
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uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
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if (RISCV_DEBUG_PLIC) {
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qemu_log("plic: read priority: irq=%d priority=%d\n",
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irq, plic->source_priority[irq]);
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}
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return plic->source_priority[irq];
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} else if (addr >= plic->pending_base && /* 1 bit per source */
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addr < plic->pending_base + (plic->num_sources >> 3))
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{
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uint32_t word = (addr - plic->pending_base) >> 2;
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if (RISCV_DEBUG_PLIC) {
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qemu_log("plic: read pending: word=%d value=%d\n",
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word, plic->pending[word]);
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}
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return plic->pending[word];
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} else if (addr >= plic->enable_base && /* 1 bit per source */
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addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
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{
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uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
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uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
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if (wordid < plic->bitfield_words) {
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if (RISCV_DEBUG_PLIC) {
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qemu_log("plic: read enable: hart%d-%c word=%d value=%x\n",
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plic->addr_config[addrid].hartid,
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mode_to_char(plic->addr_config[addrid].mode), wordid,
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plic->enable[addrid * plic->bitfield_words + wordid]);
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}
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return plic->enable[addrid * plic->bitfield_words + wordid];
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}
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} else if (addr >= plic->context_base && /* 1 bit per source */
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addr < plic->context_base + plic->num_addrs * plic->context_stride)
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{
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uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
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uint32_t contextid = (addr & (plic->context_stride - 1));
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if (contextid == 0) {
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if (RISCV_DEBUG_PLIC) {
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qemu_log("plic: read priority: hart%d-%c priority=%x\n",
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plic->addr_config[addrid].hartid,
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mode_to_char(plic->addr_config[addrid].mode),
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plic->target_priority[addrid]);
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}
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return plic->target_priority[addrid];
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} else if (contextid == 4) {
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uint32_t value = sifive_plic_claim(plic, addrid);
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if (RISCV_DEBUG_PLIC) {
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qemu_log("plic: read claim: hart%d-%c irq=%x\n",
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plic->addr_config[addrid].hartid,
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mode_to_char(plic->addr_config[addrid].mode),
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value);
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}
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sifive_plic_update(plic);
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return value;
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}
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}
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err:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Invalid register read 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return 0;
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}
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static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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SiFivePLICState *plic = opaque;
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/* writes must be 4 byte words */
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if ((addr & 0x3) != 0) {
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goto err;
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}
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if (addr >= plic->priority_base && /* 4 bytes per source */
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addr < plic->priority_base + (plic->num_sources << 2))
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{
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uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
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plic->source_priority[irq] = value & 7;
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if (RISCV_DEBUG_PLIC) {
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qemu_log("plic: write priority: irq=%d priority=%d\n",
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irq, plic->source_priority[irq]);
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}
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sifive_plic_update(plic);
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return;
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} else if (addr >= plic->pending_base && /* 1 bit per source */
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addr < plic->pending_base + (plic->num_sources >> 3))
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{
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid pending write: 0x%" HWADDR_PRIx "",
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__func__, addr);
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return;
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} else if (addr >= plic->enable_base && /* 1 bit per source */
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addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
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{
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uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
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uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
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if (wordid < plic->bitfield_words) {
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plic->enable[addrid * plic->bitfield_words + wordid] = value;
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if (RISCV_DEBUG_PLIC) {
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qemu_log("plic: write enable: hart%d-%c word=%d value=%x\n",
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plic->addr_config[addrid].hartid,
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mode_to_char(plic->addr_config[addrid].mode), wordid,
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plic->enable[addrid * plic->bitfield_words + wordid]);
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}
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return;
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}
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} else if (addr >= plic->context_base && /* 4 bytes per reg */
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addr < plic->context_base + plic->num_addrs * plic->context_stride)
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{
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uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
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uint32_t contextid = (addr & (plic->context_stride - 1));
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if (contextid == 0) {
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if (RISCV_DEBUG_PLIC) {
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qemu_log("plic: write priority: hart%d-%c priority=%x\n",
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plic->addr_config[addrid].hartid,
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mode_to_char(plic->addr_config[addrid].mode),
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plic->target_priority[addrid]);
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}
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if (value <= plic->num_priorities) {
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plic->target_priority[addrid] = value;
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sifive_plic_update(plic);
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}
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return;
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} else if (contextid == 4) {
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if (RISCV_DEBUG_PLIC) {
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qemu_log("plic: write claim: hart%d-%c irq=%x\n",
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plic->addr_config[addrid].hartid,
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mode_to_char(plic->addr_config[addrid].mode),
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(uint32_t)value);
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}
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if (value < plic->num_sources) {
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sifive_plic_set_claimed(plic, value, false);
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sifive_plic_update(plic);
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}
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return;
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}
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}
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err:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Invalid register write 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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}
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static const MemoryRegionOps sifive_plic_ops = {
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.read = sifive_plic_read,
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.write = sifive_plic_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
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}
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};
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static Property sifive_plic_properties[] = {
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DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
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DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
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DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
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DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
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DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
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DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
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DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
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DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
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DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
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DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
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DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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/*
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* parse PLIC hart/mode address offset config
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*
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* "M" 1 hart with M mode
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* "MS,MS" 2 harts, 0-1 with M and S mode
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* "M,MS,MS,MS,MS" 5 harts, 0 with M mode, 1-5 with M and S mode
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*/
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static void parse_hart_config(SiFivePLICState *plic)
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{
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int addrid, hartid, modes;
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const char *p;
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char c;
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/* count and validate hart/mode combinations */
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addrid = 0, hartid = 0, modes = 0;
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p = plic->hart_config;
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while ((c = *p++)) {
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if (c == ',') {
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addrid += ctpop8(modes);
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modes = 0;
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hartid++;
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} else {
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int m = 1 << char_to_mode(c);
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if (modes == (modes | m)) {
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error_report("plic: duplicate mode '%c' in config: %s",
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c, plic->hart_config);
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exit(1);
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}
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modes |= m;
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}
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}
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if (modes) {
|
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addrid += ctpop8(modes);
|
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}
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hartid++;
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plic->num_addrs = addrid;
|
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plic->num_harts = hartid;
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|
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/* store hart/mode combinations */
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plic->addr_config = g_new(PLICAddr, plic->num_addrs);
|
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addrid = 0, hartid = plic->hartid_base;
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p = plic->hart_config;
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while ((c = *p++)) {
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if (c == ',') {
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hartid++;
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} else {
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plic->addr_config[addrid].addrid = addrid;
|
||||
plic->addr_config[addrid].hartid = hartid;
|
||||
plic->addr_config[addrid].mode = char_to_mode(c);
|
||||
addrid++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void sifive_plic_irq_request(void *opaque, int irq, int level)
|
||||
{
|
||||
SiFivePLICState *plic = opaque;
|
||||
if (RISCV_DEBUG_PLIC) {
|
||||
qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq, level);
|
||||
}
|
||||
sifive_plic_set_pending(plic, irq, level > 0);
|
||||
sifive_plic_update(plic);
|
||||
}
|
||||
|
||||
static void sifive_plic_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
SiFivePLICState *plic = SIFIVE_PLIC(dev);
|
||||
int i;
|
||||
|
||||
memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
|
||||
TYPE_SIFIVE_PLIC, plic->aperture_size);
|
||||
parse_hart_config(plic);
|
||||
plic->bitfield_words = (plic->num_sources + 31) >> 5;
|
||||
plic->source_priority = g_new0(uint32_t, plic->num_sources);
|
||||
plic->target_priority = g_new(uint32_t, plic->num_addrs);
|
||||
plic->pending = g_new0(uint32_t, plic->bitfield_words);
|
||||
plic->claimed = g_new0(uint32_t, plic->bitfield_words);
|
||||
plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
|
||||
qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
|
||||
|
||||
/* We can't allow the supervisor to control SEIP as this would allow the
|
||||
* supervisor to clear a pending external interrupt which will result in
|
||||
* lost a interrupt in the case a PLIC is attached. The SEIP bit must be
|
||||
* hardware controlled when a PLIC is attached.
|
||||
*/
|
||||
for (i = 0; i < plic->num_harts; i++) {
|
||||
RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(plic->hartid_base + i));
|
||||
if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
|
||||
error_report("SEIP already claimed");
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
msi_nonbroken = true;
|
||||
}
|
||||
|
||||
static void sifive_plic_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
device_class_set_props(dc, sifive_plic_properties);
|
||||
dc->realize = sifive_plic_realize;
|
||||
}
|
||||
|
||||
static const TypeInfo sifive_plic_info = {
|
||||
.name = TYPE_SIFIVE_PLIC,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(SiFivePLICState),
|
||||
.class_init = sifive_plic_class_init,
|
||||
};
|
||||
|
||||
static void sifive_plic_register_types(void)
|
||||
{
|
||||
type_register_static(&sifive_plic_info);
|
||||
}
|
||||
|
||||
type_init(sifive_plic_register_types)
|
||||
|
||||
/*
|
||||
* Create PLIC device.
|
||||
*/
|
||||
DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
|
||||
uint32_t hartid_base, uint32_t num_sources,
|
||||
uint32_t num_priorities, uint32_t priority_base,
|
||||
uint32_t pending_base, uint32_t enable_base,
|
||||
uint32_t enable_stride, uint32_t context_base,
|
||||
uint32_t context_stride, uint32_t aperture_size)
|
||||
{
|
||||
DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
|
||||
assert(enable_stride == (enable_stride & -enable_stride));
|
||||
assert(context_stride == (context_stride & -context_stride));
|
||||
qdev_prop_set_string(dev, "hart-config", hart_config);
|
||||
qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
|
||||
qdev_prop_set_uint32(dev, "num-sources", num_sources);
|
||||
qdev_prop_set_uint32(dev, "num-priorities", num_priorities);
|
||||
qdev_prop_set_uint32(dev, "priority-base", priority_base);
|
||||
qdev_prop_set_uint32(dev, "pending-base", pending_base);
|
||||
qdev_prop_set_uint32(dev, "enable-base", enable_base);
|
||||
qdev_prop_set_uint32(dev, "enable-stride", enable_stride);
|
||||
qdev_prop_set_uint32(dev, "context-base", context_base);
|
||||
qdev_prop_set_uint32(dev, "context-stride", context_stride);
|
||||
qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
|
||||
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
|
||||
return dev;
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue