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target/hppa: Decode d for bb instructions

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Manipulate the shift count so that the bit to be tested
is always placed at the MSB.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-16 21:41:32 -07:00
parent 63c427c615
commit 84e224d422
2 changed files with 4 additions and 6 deletions
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4
target/hppa/insns.decode
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@ -290,8 +290,8 @@ fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd
# Conditional Branches
####
bb_sar 110000 00000 r:5 c:1 10 ........... n:1 . disp=%assemble_12
bb_imm 110001 p:5 r:5 c:1 10 ........... n:1 . disp=%assemble_12
bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
movb 110010 ..... ..... ... ........... . . @rrb_cf f=0
movbi 110011 ..... ..... ... ........... . . @rib_cf f=0