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https://github.com/Motorhead1991/qemu.git
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i386/cpu: Track a X86CPUTopoInfo directly in CPUX86State
The name of nr_modules/nr_dies are ambiguous and they mislead people. The purpose of them is to record and form the topology information. So just maintain a X86CPUTopoInfo member in CPUX86State instead. Then nr_modules and nr_dies can be dropped. As the benefit, x86 can switch to use information in CPUX86State::topo_info and get rid of the nr_cores and nr_threads in CPUState. This helps remove the dependency on qemu_init_vcpu(), so that x86 can get and use topology info earlier in x86_cpu_realizefn(); drop the comment that highlighted the depedency. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Link: https://lore.kernel.org/r/20241219110125.1266461-7-xiaoyao.li@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Xiaoyao Li
Paolo Bonzini
parent
e60cbeec19
commit
84b71a131c
4 changed files with 30 additions and 45 deletions
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@ -248,7 +248,7 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
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CPUX86State *env = &cpu->env;
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MachineState *ms = MACHINE(hotplug_dev);
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X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
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X86CPUTopoInfo topo_info;
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X86CPUTopoInfo *topo_info = &env->topo_info;
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if (!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
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error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
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@ -267,15 +267,13 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
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}
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}
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init_topo_info(&topo_info, x86ms);
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init_topo_info(topo_info, x86ms);
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if (ms->smp.modules > 1) {
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env->nr_modules = ms->smp.modules;
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set_bit(CPU_TOPOLOGY_LEVEL_MODULE, env->avail_cpu_topo);
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}
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if (ms->smp.dies > 1) {
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env->nr_dies = ms->smp.dies;
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set_bit(CPU_TOPOLOGY_LEVEL_DIE, env->avail_cpu_topo);
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}
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@ -346,12 +344,12 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
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topo_ids.module_id = cpu->module_id;
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topo_ids.core_id = cpu->core_id;
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topo_ids.smt_id = cpu->thread_id;
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cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids);
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cpu->apic_id = x86_apicid_from_topo_ids(topo_info, &topo_ids);
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}
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cpu_slot = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx);
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if (!cpu_slot) {
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x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
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x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
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error_setg(errp,
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"Invalid CPU [socket: %u, die: %u, module: %u, core: %u, thread: %u]"
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@ -374,7 +372,7 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
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/* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
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* once -smp refactoring is complete and there will be CPU private
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* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
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x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
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x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
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if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
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error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
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" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
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@ -312,11 +312,11 @@ void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
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uint64_t cpu_x86_get_msr_core_thread_count(X86CPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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CPUX86State *env = &cpu->env;
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uint64_t val;
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val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
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val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
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val = x86_threads_per_pkg(&env->topo_info); /* thread count, bits 15..0 */
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val |= x86_cores_per_pkg(&env->topo_info) << 16; /* core count, bits 31..16 */
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return val;
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}
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@ -6496,15 +6496,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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CPUState *cs = env_cpu(env);
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uint32_t limit;
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uint32_t signature[3];
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X86CPUTopoInfo topo_info;
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X86CPUTopoInfo *topo_info = &env->topo_info;
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uint32_t threads_per_pkg;
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topo_info.dies_per_pkg = env->nr_dies;
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topo_info.modules_per_die = env->nr_modules;
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topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules;
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topo_info.threads_per_core = cs->nr_threads;
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threads_per_pkg = x86_threads_per_pkg(&topo_info);
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threads_per_pkg = x86_threads_per_pkg(topo_info);
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/* Calculate & apply limits for different index ranges */
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if (index >= 0xC0000000) {
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@ -6581,12 +6576,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14);
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*eax &= ~0xFC000000;
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*eax |= max_core_ids_in_package(&topo_info) << 26;
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*eax |= max_core_ids_in_package(topo_info) << 26;
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if (host_vcpus_per_cache > threads_per_pkg) {
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*eax &= ~0x3FFC000;
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/* Share the cache at package level. */
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*eax |= max_thread_ids_for_cache(&topo_info,
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*eax |= max_thread_ids_for_cache(topo_info,
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CPU_TOPOLOGY_LEVEL_SOCKET) << 14;
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}
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}
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@ -6598,7 +6593,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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switch (count) {
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case 0: /* L1 dcache info */
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encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
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&topo_info,
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topo_info,
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eax, ebx, ecx, edx);
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if (!cpu->l1_cache_per_core) {
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*eax &= ~MAKE_64BIT_MASK(14, 12);
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@ -6606,7 +6601,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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break;
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case 1: /* L1 icache info */
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encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
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&topo_info,
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topo_info,
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eax, ebx, ecx, edx);
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if (!cpu->l1_cache_per_core) {
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*eax &= ~MAKE_64BIT_MASK(14, 12);
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@ -6614,13 +6609,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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break;
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case 2: /* L2 cache info */
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encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
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&topo_info,
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topo_info,
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eax, ebx, ecx, edx);
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break;
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case 3: /* L3 cache info */
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if (cpu->enable_l3_cache) {
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encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
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&topo_info,
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topo_info,
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eax, ebx, ecx, edx);
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break;
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}
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@ -6703,12 +6698,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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switch (count) {
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case 0:
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*eax = apicid_core_offset(&topo_info);
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*ebx = topo_info.threads_per_core;
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*eax = apicid_core_offset(topo_info);
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*ebx = topo_info->threads_per_core;
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*ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8;
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break;
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case 1:
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*eax = apicid_pkg_offset(&topo_info);
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*eax = apicid_pkg_offset(topo_info);
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*ebx = threads_per_pkg;
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*ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8;
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break;
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@ -6734,7 +6729,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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break;
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}
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encode_topo_cpuid1f(env, count, &topo_info, eax, ebx, ecx, edx);
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encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx);
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break;
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case 0xD: {
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/* Processor Extended State */
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@ -7037,7 +7032,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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* thread ID within a package".
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* Bits 7:0 is "The number of threads in the package is NC+1"
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*/
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*ecx = (apicid_pkg_offset(&topo_info) << 12) |
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*ecx = (apicid_pkg_offset(topo_info) << 12) |
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(threads_per_pkg - 1);
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} else {
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*ecx = 0;
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@ -7066,19 +7061,19 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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switch (count) {
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case 0: /* L1 dcache info */
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encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
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&topo_info, eax, ebx, ecx, edx);
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topo_info, eax, ebx, ecx, edx);
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break;
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case 1: /* L1 icache info */
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encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
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&topo_info, eax, ebx, ecx, edx);
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topo_info, eax, ebx, ecx, edx);
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break;
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case 2: /* L2 cache info */
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encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
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&topo_info, eax, ebx, ecx, edx);
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topo_info, eax, ebx, ecx, edx);
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break;
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case 3: /* L3 cache info */
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encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
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&topo_info, eax, ebx, ecx, edx);
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topo_info, eax, ebx, ecx, edx);
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break;
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default: /* end of info */
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*eax = *ebx = *ecx = *edx = 0;
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@ -7090,7 +7085,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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break;
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case 0x8000001E:
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if (cpu->core_id <= 255) {
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encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx);
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encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx);
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} else {
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*eax = 0;
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*ebx = 0;
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@ -7997,17 +7992,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
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* fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
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* based on inputs (sockets,cores,threads), it is still better to give
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* users a warning.
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*
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* NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
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* cs->nr_threads hasn't be populated yet and the checking is incorrect.
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*/
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if (IS_AMD_CPU(env) &&
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!(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
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cs->nr_threads > 1) {
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env->topo_info.threads_per_core > 1) {
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warn_report_once("This family of AMD CPU doesn't support "
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"hyperthreading(%d). Please configure -smp "
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"options properly or try enabling topoext "
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"feature.", cs->nr_threads);
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"feature.", env->topo_info.threads_per_core);
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}
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#ifndef CONFIG_USER_ONLY
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@ -8168,8 +8160,7 @@ static void x86_cpu_init_default_topo(X86CPU *cpu)
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{
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CPUX86State *env = &cpu->env;
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env->nr_modules = 1;
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env->nr_dies = 1;
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env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1};
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/* thread, core and socket levels are set by default. */
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set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo);
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@ -2068,11 +2068,7 @@ typedef struct CPUArchState {
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TPRAccess tpr_access_type;
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/* Number of dies within this CPU package. */
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unsigned nr_dies;
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/* Number of modules within one die. */
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unsigned nr_modules;
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X86CPUTopoInfo topo_info;
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/* Bitmap of available CPU topology levels for this CPU. */
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DECLARE_BITMAP(avail_cpu_topo, CPU_TOPOLOGY_LEVEL__MAX);
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