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tcg/riscv64: Fold the ext{8,16,32}[us] cases into {s}extract

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Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-26 00:17:20 -08:00
parent 94d593941b
commit 841e2c5257
2 changed files with 69 additions and 4 deletions
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39
tcg/riscv/tcg-target-has.h
View file

@ -16,8 +16,8 @@
#define TCG_TARGET_HAS_div2_i32 0 #define TCG_TARGET_HAS_div2_i32 0
#define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_deposit_i32 0 #define TCG_TARGET_HAS_deposit_i32 0
#define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_extract_i32 1
#define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_sextract_i32 1
#define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1
@ -50,8 +50,8 @@
#define TCG_TARGET_HAS_div2_i64 0 #define TCG_TARGET_HAS_div2_i64 0
#define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_deposit_i64 0 #define TCG_TARGET_HAS_deposit_i64 0
#define TCG_TARGET_HAS_extract_i64 0 #define TCG_TARGET_HAS_extract_i64 1
#define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_sextract_i64 1
#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_extr_i64_i32 1 #define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_ext8s_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1
@ -109,4 +109,35 @@
#define TCG_TARGET_HAS_tst_vec 0 #define TCG_TARGET_HAS_tst_vec 0
static inline bool
tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
{
if (ofs == 0) {
switch (len) {
case 16:
return cpuinfo & CPUINFO_ZBB;
case 32:
return (cpuinfo & CPUINFO_ZBA) && type == TCG_TYPE_I64;
}
}
return false;
}
#define TCG_TARGET_extract_valid tcg_target_extract_valid
static inline bool
tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
{
if (ofs == 0) {
switch (len) {
case 8:
case 16:
return cpuinfo & CPUINFO_ZBB;
case 32:
return type == TCG_TYPE_I64;
}
}
return false;
}
#define TCG_TARGET_sextract_valid tcg_target_sextract_valid
#endif #endif

34
tcg/riscv/tcg-target.c.inc
View file

@ -2343,6 +2343,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_mb(s, a0); tcg_out_mb(s, a0);
break; break;
case INDEX_op_extract_i64:
if (a2 == 0 && args[3] == 32) {
tcg_out_ext32u(s, a0, a1);
break;
}
/* FALLTHRU */
case INDEX_op_extract_i32:
if (a2 == 0 && args[3] == 16) {
tcg_out_ext16u(s, a0, a1);
} else {
g_assert_not_reached();
}
break;
case INDEX_op_sextract_i64:
if (a2 == 0 && args[3] == 32) {
tcg_out_ext32s(s, a0, a1);
break;
}
/* FALLTHRU */
case INDEX_op_sextract_i32:
if (a2 == 0 && args[3] == 8) {
tcg_out_ext8s(s, TCG_TYPE_REG, a0, a1);
} else if (a2 == 0 && args[3] == 16) {
tcg_out_ext16s(s, TCG_TYPE_REG, a0, a1);
} else {
g_assert_not_reached();
}
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64: case INDEX_op_mov_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_call: /* Always emitted via tcg_out_call. */
@ -2620,6 +2650,10 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_extrl_i64_i32: case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32: case INDEX_op_extrh_i64_i32:
case INDEX_op_ext_i32_i64: case INDEX_op_ext_i32_i64:
case INDEX_op_extract_i32:
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i32:
case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i32:
case INDEX_op_bswap16_i64: case INDEX_op_bswap16_i64: