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target/riscv: Adjust csr write mask with XLEN

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Write mask is representing the bits we care about.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-11-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei 2022-01-20 20:20:37 +08:00 • committed by Alistair Francis
parent 47bdec821b
commit 83b519b8a4
2 changed files with 10 additions and 5 deletions
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12
target/riscv/insn_trans/trans_rvi.c.inc
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@ -924,7 +924,8 @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc,
static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
{
if (get_xl(ctx) < MXL_RV128) {
RISCVMXL xl = get_xl(ctx);
if (xl < MXL_RV128) {
TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
/*
@ -935,7 +936,8 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
return do_csrw(ctx, a->csr, src);
}
TCGv mask = tcg_constant_tl(-1);
TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
(target_ulong)-1);
return do_csrrw(ctx, a->rd, a->csr, src, mask);
} else {
TCGv srcl = get_gpr(ctx, a->rs1, EXT_NONE);
@ -1013,7 +1015,8 @@ static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
{
if (get_xl(ctx) < MXL_RV128) {
RISCVMXL xl = get_xl(ctx);
if (xl < MXL_RV128) {
TCGv src = tcg_constant_tl(a->rs1);
/*
@ -1024,7 +1027,8 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
return do_csrw(ctx, a->csr, src);
}
TCGv mask = tcg_constant_tl(-1);
TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
(target_ulong)-1);
return do_csrrw(ctx, a->rd, a->csr, src, mask);
} else {
TCGv src = tcg_constant_tl(a->rs1);