mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-09 10:34:58 -06:00
sparc64 fixes (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1514 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
b7c7b18129
commit
8346901560
15 changed files with 1053 additions and 284 deletions
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@ -139,7 +139,7 @@ int load_elf(const char *filename, uint8_t *addr)
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if (find_phdr64(&ehdr64, fd, &phdr, PT_LOAD))
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goto error;
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retval = read_program64(fd, &phdr, addr, ehdr64.e_entry);
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retval = read_program64(fd, &phdr, phys_ram_base + ehdr64.e_entry, ehdr64.e_entry);
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if (retval < 0)
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goto error;
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load_symbols64(&ehdr64, fd);
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247
hw/pci.c
247
hw/pci.c
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@ -1291,6 +1291,253 @@ PCIBus *pci_pmac_init(void)
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return s;
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}
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/* Ultrasparc APB PCI host */
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static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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PCIBus *s = opaque;
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int i;
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for (i = 11; i < 32; i++) {
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if ((val & (1 << i)) != 0)
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break;
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}
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s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
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}
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static uint32_t pci_apb_config_readl (void *opaque,
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target_phys_addr_t addr)
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{
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PCIBus *s = opaque;
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uint32_t val;
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int devfn;
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devfn = (s->config_reg >> 8) & 0xFF;
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val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC);
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return val;
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}
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static CPUWriteMemoryFunc *pci_apb_config_write[] = {
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&pci_apb_config_writel,
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&pci_apb_config_writel,
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&pci_apb_config_writel,
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};
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static CPUReadMemoryFunc *pci_apb_config_read[] = {
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&pci_apb_config_readl,
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&pci_apb_config_readl,
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&pci_apb_config_readl,
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};
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static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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//PCIBus *s = opaque;
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switch (addr & 0x3f) {
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case 0x00: // Control/Status
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case 0x10: // AFSR
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case 0x18: // AFAR
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case 0x20: // Diagnostic
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case 0x28: // Target address space
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// XXX
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default:
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break;
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}
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}
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static uint32_t apb_config_readl (void *opaque,
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target_phys_addr_t addr)
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{
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//PCIBus *s = opaque;
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uint32_t val;
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switch (addr & 0x3f) {
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case 0x00: // Control/Status
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case 0x10: // AFSR
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case 0x18: // AFAR
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case 0x20: // Diagnostic
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case 0x28: // Target address space
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// XXX
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default:
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val = 0;
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break;
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}
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return val;
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}
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static CPUWriteMemoryFunc *apb_config_write[] = {
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&apb_config_writel,
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&apb_config_writel,
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&apb_config_writel,
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};
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static CPUReadMemoryFunc *apb_config_read[] = {
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&apb_config_readl,
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&apb_config_readl,
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&apb_config_readl,
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};
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static void pci_apb_writeb (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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PCIBus *s = opaque;
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pci_data_write(s, addr & 7, val, 1);
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}
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static void pci_apb_writew (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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PCIBus *s = opaque;
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pci_data_write(s, addr & 7, val, 2);
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}
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static void pci_apb_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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PCIBus *s = opaque;
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pci_data_write(s, addr & 7, val, 4);
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}
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static uint32_t pci_apb_readb (void *opaque, target_phys_addr_t addr)
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{
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PCIBus *s = opaque;
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uint32_t val;
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val = pci_data_read(s, addr & 7, 1);
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return val;
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}
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static uint32_t pci_apb_readw (void *opaque, target_phys_addr_t addr)
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{
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PCIBus *s = opaque;
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uint32_t val;
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val = pci_data_read(s, addr & 7, 2);
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return val;
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}
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static uint32_t pci_apb_readl (void *opaque, target_phys_addr_t addr)
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{
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PCIBus *s = opaque;
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uint32_t val;
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val = pci_data_read(s, addr, 4);
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return val;
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}
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static CPUWriteMemoryFunc *pci_apb_write[] = {
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&pci_apb_writeb,
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&pci_apb_writew,
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&pci_apb_writel,
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};
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static CPUReadMemoryFunc *pci_apb_read[] = {
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&pci_apb_readb,
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&pci_apb_readw,
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&pci_apb_readl,
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};
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static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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cpu_outb(NULL, addr & 0xffff, val);
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}
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static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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cpu_outw(NULL, addr & 0xffff, val);
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}
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static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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cpu_outl(NULL, addr & 0xffff, val);
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}
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static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inb(NULL, addr & 0xffff);
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return val;
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}
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static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inw(NULL, addr & 0xffff);
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return val;
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}
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static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inl(NULL, addr & 0xffff);
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return val;
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}
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static CPUWriteMemoryFunc *pci_apb_iowrite[] = {
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&pci_apb_iowriteb,
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&pci_apb_iowritew,
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&pci_apb_iowritel,
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};
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static CPUReadMemoryFunc *pci_apb_ioread[] = {
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&pci_apb_ioreadb,
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&pci_apb_ioreadw,
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&pci_apb_ioreadl,
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};
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PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base)
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{
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PCIBus *s;
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PCIDevice *d;
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int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
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/* Ultrasparc APB main bus */
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s = pci_register_bus();
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s->set_irq = pci_set_irq_simple;
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pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read,
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pci_apb_config_write, s);
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apb_config = cpu_register_io_memory(0, apb_config_read,
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apb_config_write, s);
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pci_mem_data = cpu_register_io_memory(0, pci_apb_read,
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pci_apb_write, s);
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pci_ioport = cpu_register_io_memory(0, pci_apb_ioread,
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pci_apb_iowrite, s);
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cpu_register_physical_memory(special_base + 0x2000ULL, 0x40, apb_config);
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cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10, pci_mem_config);
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cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, pci_ioport);
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cpu_register_physical_memory(mem_base, 0x10000000, pci_mem_data); // XXX size should be 4G-prom
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d = pci_register_device(s, "Advanced PCI Bus", sizeof(PCIDevice),
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-1, NULL, NULL);
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d->config[0x00] = 0x8e; // vendor_id : Sun
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d->config[0x01] = 0x10;
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d->config[0x02] = 0x00; // device_id
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d->config[0x03] = 0xa0;
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d->config[0x04] = 0x06; // command = bus master, pci mem
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d->config[0x05] = 0x00;
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d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
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d->config[0x07] = 0x03; // status = medium devsel
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d->config[0x08] = 0x00; // revision
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d->config[0x09] = 0x00; // programming i/f
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d->config[0x0A] = 0x00; // class_sub = pci host
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d->config[0x0B] = 0x06; // class_base = PCI_bridge
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d->config[0x0D] = 0x10; // latency_timer
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d->config[0x0E] = 0x00; // header_type
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return s;
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}
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/***********************************************************/
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/* generic PCI irq support */
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287
hw/sun4u.c
287
hw/sun4u.c
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@ -22,23 +22,18 @@
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#include "m48t08.h"
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#include "m48t59.h"
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#define KERNEL_LOAD_ADDR 0x00004000
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#define CMDLINE_ADDR 0x007ff000
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#define INITRD_LOAD_ADDR 0x00800000
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#define PROM_ADDR 0xffd00000
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#define KERNEL_LOAD_ADDR 0x00404000
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#define CMDLINE_ADDR 0x003ff000
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#define INITRD_LOAD_ADDR 0x00300000
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#define PROM_ADDR 0x1fff0000000ULL
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#define APB_SPECIAL_BASE 0x1fe00000000ULL
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#define APB_MEM_BASE 0x1ff00000000ULL
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#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
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#define PROM_FILENAMEB "proll-sparc64.bin"
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#define PROM_FILENAMEE "proll-sparc64.elf"
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#define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */
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#define PHYS_JJ_IDPROM_OFF 0x1FD8
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#define PHYS_JJ_EEPROM_SIZE 0x2000
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// IRQs are not PIL ones, but master interrupt controller register
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// bits
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#define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */
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#define PHYS_JJ_MS_KBD_IRQ 14
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#define PHYS_JJ_SER 0x71100000 /* Serial */
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#define PHYS_JJ_SER_IRQ 15
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#define NVRAM_SIZE 0x2000
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/* TSC handling */
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@ -70,79 +65,170 @@ void DMA_register_channel (int nchan,
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{
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}
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static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value)
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/* NVRAM helpers */
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void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
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{
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m48t08_write(nvram, addr++, (value >> 8) & 0xff);
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m48t08_write(nvram, addr++, value & 0xff);
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m48t59_set_addr(nvram, addr);
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m48t59_write(nvram, value);
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}
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static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value)
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uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
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{
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m48t08_write(nvram, addr++, value >> 24);
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m48t08_write(nvram, addr++, (value >> 16) & 0xff);
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m48t08_write(nvram, addr++, (value >> 8) & 0xff);
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m48t08_write(nvram, addr++, value & 0xff);
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m48t59_set_addr(nvram, addr);
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return m48t59_read(nvram);
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}
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static void nvram_set_string (m48t08_t *nvram, uint32_t addr,
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void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
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{
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m48t59_set_addr(nvram, addr);
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m48t59_write(nvram, value >> 8);
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m48t59_set_addr(nvram, addr + 1);
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m48t59_write(nvram, value & 0xFF);
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}
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uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
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{
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uint16_t tmp;
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m48t59_set_addr(nvram, addr);
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tmp = m48t59_read(nvram) << 8;
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m48t59_set_addr(nvram, addr + 1);
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tmp |= m48t59_read(nvram);
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return tmp;
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}
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void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
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{
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m48t59_set_addr(nvram, addr);
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m48t59_write(nvram, value >> 24);
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m48t59_set_addr(nvram, addr + 1);
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m48t59_write(nvram, (value >> 16) & 0xFF);
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m48t59_set_addr(nvram, addr + 2);
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m48t59_write(nvram, (value >> 8) & 0xFF);
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m48t59_set_addr(nvram, addr + 3);
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m48t59_write(nvram, value & 0xFF);
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}
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uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
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{
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uint32_t tmp;
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m48t59_set_addr(nvram, addr);
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tmp = m48t59_read(nvram) << 24;
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m48t59_set_addr(nvram, addr + 1);
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tmp |= m48t59_read(nvram) << 16;
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m48t59_set_addr(nvram, addr + 2);
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tmp |= m48t59_read(nvram) << 8;
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m48t59_set_addr(nvram, addr + 3);
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tmp |= m48t59_read(nvram);
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return tmp;
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}
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void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
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const unsigned char *str, uint32_t max)
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{
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unsigned int i;
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int i;
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for (i = 0; i < max && str[i] != '\0'; i++) {
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m48t08_write(nvram, addr + i, str[i]);
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m48t59_set_addr(nvram, addr + i);
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m48t59_write(nvram, str[i]);
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}
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m48t08_write(nvram, addr + max - 1, '\0');
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m48t59_set_addr(nvram, addr + max - 1);
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m48t59_write(nvram, '\0');
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}
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static m48t08_t *nvram;
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int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
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{
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int i;
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memset(dst, 0, max);
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for (i = 0; i < max; i++) {
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dst[i] = NVRAM_get_byte(nvram, addr + i);
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if (dst[i] == '\0')
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break;
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}
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return i;
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}
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static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
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{
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uint16_t tmp;
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uint16_t pd, pd1, pd2;
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tmp = prev >> 8;
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pd = prev ^ value;
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pd1 = pd & 0x000F;
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pd2 = ((pd >> 4) & 0x000F) ^ pd1;
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tmp ^= (pd1 << 3) | (pd1 << 8);
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tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
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return tmp;
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}
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uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
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{
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uint32_t i;
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uint16_t crc = 0xFFFF;
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int odd;
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odd = count & 1;
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count &= ~1;
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for (i = 0; i != count; i++) {
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crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
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}
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if (odd) {
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crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
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}
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return crc;
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}
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extern int nographic;
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static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline,
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int boot_device, uint32_t RAM_size,
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uint32_t kernel_size,
|
||||
int width, int height, int depth)
|
||||
int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
|
||||
const unsigned char *arch,
|
||||
uint32_t RAM_size, int boot_device,
|
||||
uint32_t kernel_image, uint32_t kernel_size,
|
||||
const char *cmdline,
|
||||
uint32_t initrd_image, uint32_t initrd_size,
|
||||
uint32_t NVRAM_image,
|
||||
int width, int height, int depth)
|
||||
{
|
||||
unsigned char tmp = 0;
|
||||
int i, j;
|
||||
uint16_t crc;
|
||||
|
||||
// Try to match PPC NVRAM
|
||||
nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
|
||||
nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */
|
||||
// NVRAM_size, arch not applicable
|
||||
m48t08_write(nvram, 0x2F, nographic & 0xff);
|
||||
nvram_set_lword(nvram, 0x30, RAM_size);
|
||||
m48t08_write(nvram, 0x34, boot_device & 0xff);
|
||||
nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
|
||||
nvram_set_lword(nvram, 0x3C, kernel_size);
|
||||
/* Set parameters for Open Hack'Ware BIOS */
|
||||
NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
|
||||
NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
|
||||
NVRAM_set_word(nvram, 0x14, NVRAM_size);
|
||||
NVRAM_set_string(nvram, 0x20, arch, 16);
|
||||
NVRAM_set_byte(nvram, 0x2f, nographic & 0xff);
|
||||
NVRAM_set_lword(nvram, 0x30, RAM_size);
|
||||
NVRAM_set_byte(nvram, 0x34, boot_device);
|
||||
NVRAM_set_lword(nvram, 0x38, kernel_image);
|
||||
NVRAM_set_lword(nvram, 0x3C, kernel_size);
|
||||
if (cmdline) {
|
||||
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
|
||||
nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
||||
nvram_set_lword(nvram, 0x44, strlen(cmdline));
|
||||
/* XXX: put the cmdline in NVRAM too ? */
|
||||
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
|
||||
NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
||||
NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
|
||||
} else {
|
||||
NVRAM_set_lword(nvram, 0x40, 0);
|
||||
NVRAM_set_lword(nvram, 0x44, 0);
|
||||
}
|
||||
// initrd_image, initrd_size passed differently
|
||||
nvram_set_word(nvram, 0x54, width);
|
||||
nvram_set_word(nvram, 0x56, height);
|
||||
nvram_set_word(nvram, 0x58, depth);
|
||||
NVRAM_set_lword(nvram, 0x48, initrd_image);
|
||||
NVRAM_set_lword(nvram, 0x4C, initrd_size);
|
||||
NVRAM_set_lword(nvram, 0x50, NVRAM_image);
|
||||
|
||||
// Sun4m specific use
|
||||
i = 0x1fd8;
|
||||
m48t08_write(nvram, i++, 0x01);
|
||||
m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */
|
||||
j = 0;
|
||||
m48t08_write(nvram, i++, macaddr[j++]);
|
||||
m48t08_write(nvram, i++, macaddr[j++]);
|
||||
m48t08_write(nvram, i++, macaddr[j++]);
|
||||
m48t08_write(nvram, i++, macaddr[j++]);
|
||||
m48t08_write(nvram, i++, macaddr[j++]);
|
||||
m48t08_write(nvram, i, macaddr[j]);
|
||||
NVRAM_set_word(nvram, 0x54, width);
|
||||
NVRAM_set_word(nvram, 0x56, height);
|
||||
NVRAM_set_word(nvram, 0x58, depth);
|
||||
crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
|
||||
NVRAM_set_word(nvram, 0xFC, crc);
|
||||
|
||||
/* Calculate checksum */
|
||||
for (i = 0x1fd8; i < 0x1fe7; i++) {
|
||||
tmp ^= m48t08_read(nvram, i);
|
||||
}
|
||||
m48t08_write(nvram, 0x1fe7, tmp);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void pic_info()
|
||||
|
|
@ -157,15 +243,7 @@ void pic_set_irq(int irq, int level)
|
|||
{
|
||||
}
|
||||
|
||||
void vga_update_display()
|
||||
{
|
||||
}
|
||||
|
||||
void vga_invalidate_display()
|
||||
{
|
||||
}
|
||||
|
||||
void vga_screen_dump(const char *filename)
|
||||
void pic_set_irq_new(void *opaque, int irq, int level)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -173,6 +251,18 @@ void qemu_system_powerdown(void)
|
|||
{
|
||||
}
|
||||
|
||||
static const int ide_iobase[2] = { 0x1f0, 0x170 };
|
||||
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
|
||||
static const int ide_irq[2] = { 14, 15 };
|
||||
|
||||
static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
|
||||
static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
|
||||
|
||||
static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
|
||||
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
|
||||
|
||||
static fdctrl_t *floppy_controller;
|
||||
|
||||
/* Sun4u hardware initialisation */
|
||||
static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
|
||||
DisplayState *ds, const char **fd_filename, int snapshot,
|
||||
|
|
@ -180,21 +270,18 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
|
|||
const char *initrd_filename)
|
||||
{
|
||||
char buf[1024];
|
||||
m48t59_t *nvram;
|
||||
int ret, linux_boot;
|
||||
unsigned int i;
|
||||
long vram_size = 0x100000, prom_offset, initrd_size, kernel_size;
|
||||
long prom_offset, initrd_size, kernel_size;
|
||||
PCIBus *pci_bus;
|
||||
|
||||
linux_boot = (kernel_filename != NULL);
|
||||
|
||||
/* allocate RAM */
|
||||
cpu_register_physical_memory(0, ram_size, 0);
|
||||
|
||||
nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE);
|
||||
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
||||
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
||||
slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]);
|
||||
|
||||
prom_offset = ram_size + vram_size;
|
||||
prom_offset = ram_size + vga_ram_size;
|
||||
|
||||
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE);
|
||||
ret = load_elf(buf, phys_ram_base + prom_offset);
|
||||
|
|
@ -211,6 +298,7 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
|
|||
prom_offset | IO_MEM_ROM);
|
||||
|
||||
kernel_size = 0;
|
||||
initrd_size = 0;
|
||||
if (linux_boot) {
|
||||
kernel_size = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
||||
if (kernel_size < 0)
|
||||
|
|
@ -224,7 +312,6 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
|
|||
}
|
||||
|
||||
/* load initrd */
|
||||
initrd_size = 0;
|
||||
if (initrd_filename) {
|
||||
initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
|
||||
if (initrd_size < 0) {
|
||||
|
|
@ -244,7 +331,41 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
|
|||
}
|
||||
}
|
||||
}
|
||||
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth);
|
||||
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE);
|
||||
isa_mem_base = VGA_BASE;
|
||||
vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size,
|
||||
vga_ram_size, 0, 0);
|
||||
cpu_register_physical_memory(VGA_BASE, vga_ram_size, ram_size);
|
||||
//pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
|
||||
|
||||
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
|
||||
if (serial_hds[i]) {
|
||||
serial_init(serial_io[i], serial_irq[i], serial_hds[i]);
|
||||
}
|
||||
}
|
||||
|
||||
for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
|
||||
if (parallel_hds[i]) {
|
||||
parallel_init(parallel_io[i], parallel_irq[i], parallel_hds[i]);
|
||||
}
|
||||
}
|
||||
|
||||
for(i = 0; i < nb_nics; i++) {
|
||||
pci_ne2000_init(pci_bus, &nd_table[i]);
|
||||
}
|
||||
|
||||
pci_cmd646_ide_init(pci_bus, bs_table, 1);
|
||||
kbd_init();
|
||||
floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table);
|
||||
nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE);
|
||||
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
|
||||
KERNEL_LOAD_ADDR, kernel_size,
|
||||
kernel_cmdline,
|
||||
INITRD_LOAD_ADDR, initrd_size,
|
||||
/* XXX: need an option to load a NVRAM image */
|
||||
0,
|
||||
graphic_width, graphic_height, graphic_depth);
|
||||
|
||||
}
|
||||
|
||||
QEMUMachine sun4u_machine = {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue