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target/riscv: rvb: generalized reverse

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Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-13-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2021-05-06 00:06:13 +08:00 • committed by Alistair Francis
parent e58529a8d0
commit 831ec7f3d1
6 changed files with 132 additions and 0 deletions
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28
target/riscv/translate.c
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@ -627,6 +627,28 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_not_tl(ret, ret);
}
static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
{
TCGv source1 = tcg_temp_new();
TCGv source2;
gen_get_gpr(source1, a->rs1);
if (a->shamt == (TARGET_LONG_BITS - 8)) {
/* rev8, byte swaps */
tcg_gen_bswap_tl(source1, source1);
} else {
source2 = tcg_temp_new();
tcg_gen_movi_tl(source2, a->shamt);
gen_helper_grev(source1, source1, source2);
tcg_temp_free(source2);
}
gen_set_gpr(a->rd, source1);
tcg_temp_free(source1);
return true;
}
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@ -699,6 +721,12 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free_i32(t2);
}
static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_ext32u_tl(arg1, arg1);
gen_helper_grev(ret, arg1, arg2);
}
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{