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target/cris: Reindent mmu.c

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Fix all of the coding style errors in this file at once.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2019-05-06 20:58:57 -07:00
parent 2fc0cc0e1e
commit 81ff3de728
1 changed files with 237 additions and 242 deletions
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95
target/cris/mmu.c
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@ -43,8 +43,9 @@ static inline unsigned int compute_polynom(unsigned int sr)
unsigned int f; unsigned int f;
f = 0; f = 0;
for (i = 0; i < 16; i++) for (i = 0; i < 16; i++) {
f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1); f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
}
return f; return f;
} }
@ -75,10 +76,11 @@ static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg)
uint32_t base; uint32_t base;
int i; int i;
if (seg < 8) if (seg < 8) {
base = env->sregs[SFR_RW_MM_KBASE_LO]; base = env->sregs[SFR_RW_MM_KBASE_LO];
else } else {
base = env->sregs[SFR_RW_MM_KBASE_HI]; base = env->sregs[SFR_RW_MM_KBASE_HI];
}
i = seg & 7; i = seg & 7;
base >>= i * 4; base >>= i * 4;
@ -87,6 +89,7 @@ static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg)
base <<= 28; base <<= 28;
return base; return base;
} }
/* Used by the tlb decoder. */ /* Used by the tlb decoder. */
#define EXTRACT_FIELD(src, start, end) \ #define EXTRACT_FIELD(src, start, end) \
(((src) >> start) & ((1 << (end - start + 1)) - 1)) (((src) >> start) & ((1 << (end - start + 1)) - 1))
@ -119,7 +122,7 @@ static void dump_tlb(CPUCRISState *env, int mmu)
tlb_vpn = EXTRACT_FIELD(hi, 13, 31); tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
tlb_pfn = EXTRACT_FIELD(lo, 13, 31); tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n", printf("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
set, idx, hi, lo, tlb_vpn, tlb_pfn); set, idx, hi, lo, tlb_vpn, tlb_pfn);
} }
} }
@ -149,10 +152,17 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
pid = env->pregs[PR_PID] & 0xff; pid = env->pregs[PR_PID] & 0xff;
switch (rw) { switch (rw) {
case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break; case 2:
case 1: rwcause = CRIS_MMU_ERR_WRITE; break; rwcause = CRIS_MMU_ERR_EXEC;
mmu = 0;
break;
case 1:
rwcause = CRIS_MMU_ERR_WRITE;
break;
default: default:
case 0: rwcause = CRIS_MMU_ERR_READ; break; case 0:
rwcause = CRIS_MMU_ERR_READ;
break;
} }
/* I exception vectors 4 - 7, D 8 - 11. */ /* I exception vectors 4 - 7, D 8 - 11. */
@ -160,25 +170,12 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
vpage = vaddr >> 13; vpage = vaddr >> 13;
/* We know the index which to check on each set. /*
Scan both I and D. */ * We know the index which to check on each set.
#if 0 * Scan both I and D.
for (set = 0; set < 4; set++) { */
for (idx = 0; idx < 16; idx++) {
lo = env->tlbsets[mmu][set][idx].lo;
hi = env->tlbsets[mmu][set][idx].hi;
tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
set, idx, hi, lo, tlb_vpn, tlb_pfn);
}
}
#endif
idx = vpage & 15; idx = vpage & 15;
for (set = 0; set < 4; set++) for (set = 0; set < 4; set++) {
{
lo = env->tlbsets[mmu][set][idx].lo; lo = env->tlbsets[mmu][set][idx].lo;
hi = env->tlbsets[mmu][set][idx].hi; hi = env->tlbsets[mmu][set][idx].hi;
@ -188,8 +185,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n", D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
mmu, set, idx, tlb_vpn, vpage, lo, hi); mmu, set, idx, tlb_vpn, vpage, lo, hi);
if ((tlb_g || (tlb_pid == pid)) if ((tlb_g || (tlb_pid == pid)) && tlb_vpn == vpage) {
&& tlb_vpn == vpage) {
match = 1; match = 1;
break; break;
} }
@ -209,33 +205,33 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
tlb_x = EXTRACT_FIELD(lo, 0, 0); tlb_x = EXTRACT_FIELD(lo, 0, 0);
/* /*
set_exception_vector(0x04, i_mmu_refill); * set_exception_vector(0x04, i_mmu_refill);
set_exception_vector(0x05, i_mmu_invalid); * set_exception_vector(0x05, i_mmu_invalid);
set_exception_vector(0x06, i_mmu_access); * set_exception_vector(0x06, i_mmu_access);
set_exception_vector(0x07, i_mmu_execute); * set_exception_vector(0x07, i_mmu_execute);
set_exception_vector(0x08, d_mmu_refill); * set_exception_vector(0x08, d_mmu_refill);
set_exception_vector(0x09, d_mmu_invalid); * set_exception_vector(0x09, d_mmu_invalid);
set_exception_vector(0x0a, d_mmu_access); * set_exception_vector(0x0a, d_mmu_access);
set_exception_vector(0x0b, d_mmu_write); * set_exception_vector(0x0b, d_mmu_write);
*/ */
if (cfg_k && tlb_k && usermode) { if (cfg_k && tlb_k && usermode) {
D(printf ("tlb: kernel protected %x lo=%x pc=%x\n", D(printf("tlb: kernel protected %x lo=%x pc=%x\n",
vaddr, lo, env->pc)); vaddr, lo, env->pc));
match = 0; match = 0;
res->bf_vec = vect_base + 2; res->bf_vec = vect_base + 2;
} else if (rw == 1 && cfg_w && !tlb_w) { } else if (rw == 1 && cfg_w && !tlb_w) {
D(printf ("tlb: write protected %x lo=%x pc=%x\n", D(printf("tlb: write protected %x lo=%x pc=%x\n",
vaddr, lo, env->pc)); vaddr, lo, env->pc));
match = 0; match = 0;
/* write accesses never go through the I mmu. */ /* write accesses never go through the I mmu. */
res->bf_vec = vect_base + 3; res->bf_vec = vect_base + 3;
} else if (rw == 2 && cfg_x && !tlb_x) { } else if (rw == 2 && cfg_x && !tlb_x) {
D(printf ("tlb: exec protected %x lo=%x pc=%x\n", D(printf("tlb: exec protected %x lo=%x pc=%x\n",
vaddr, lo, env->pc)); vaddr, lo, env->pc));
match = 0; match = 0;
res->bf_vec = vect_base + 3; res->bf_vec = vect_base + 3;
} else if (cfg_v && !tlb_v) { } else if (cfg_v && !tlb_v) {
D(printf ("tlb: invalid %x\n", vaddr)); D(printf("tlb: invalid %x\n", vaddr));
match = 0; match = 0;
res->bf_vec = vect_base + 1; res->bf_vec = vect_base + 1;
} }
@ -243,13 +239,15 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
res->prot = 0; res->prot = 0;
if (match) { if (match) {
res->prot |= PAGE_READ; res->prot |= PAGE_READ;
if (tlb_w) if (tlb_w) {
res->prot |= PAGE_WRITE; res->prot |= PAGE_WRITE;
if (mmu == 0 && (cfg_x || tlb_x)) }
if (mmu == 0 && (cfg_x || tlb_x)) {
res->prot |= PAGE_EXEC; res->prot |= PAGE_EXEC;
} }
else } else {
D(dump_tlb(env, mmu)); D(dump_tlb(env, mmu));
}
} else { } else {
/* If refill, provide a randomized set. */ /* If refill, provide a randomized set. */
set = env->mmu_rand_lfsr & 3; set = env->mmu_rand_lfsr & 3;
@ -274,7 +272,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc)); D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
} }
D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x" D(printf("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
" %x cause=%x sel=%x sp=%x %x %x\n", " %x cause=%x sel=%x sp=%x %x %x\n",
__func__, rw, match, env->pc, __func__, rw, match, env->pc,
vaddr, vpage, vaddr, vpage,
@ -301,8 +299,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
pid &= 0xff; pid &= 0xff;
for (mmu = 0; mmu < 2; mmu++) { for (mmu = 0; mmu < 2; mmu++) {
for (set = 0; set < 4; set++) for (set = 0; set < 4; set++) {
{
for (idx = 0; idx < 16; idx++) { for (idx = 0; idx < 16; idx++) {
lo = env->tlbsets[mmu][set][idx].lo; lo = env->tlbsets[mmu][set][idx].lo;
hi = env->tlbsets[mmu][set][idx].hi; hi = env->tlbsets[mmu][set][idx].hi;
@ -314,8 +311,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
if (tlb_v && !tlb_g && (tlb_pid == pid)) { if (tlb_v && !tlb_g && (tlb_pid == pid)) {
vaddr = tlb_vpn << TARGET_PAGE_BITS; vaddr = tlb_vpn << TARGET_PAGE_BITS;
D_LOG("flush pid=%x vaddr=%x\n", D_LOG("flush pid=%x vaddr=%x\n", pid, vaddr);
pid, vaddr);
tlb_flush_page(CPU(cpu), vaddr); tlb_flush_page(CPU(cpu), vaddr);
} }
} }
@ -332,7 +328,7 @@ int cris_mmu_translate(struct cris_mmu_result *res,
int is_user = mmu_idx == MMU_USER_IDX; int is_user = mmu_idx == MMU_USER_IDX;
uint32_t old_srs; uint32_t old_srs;
old_srs= env->pregs[PR_SRS]; old_srs = env->pregs[PR_SRS];
/* rw == 2 means exec, map the access to the insn mmu. */ /* rw == 2 means exec, map the access to the insn mmu. */
env->pregs[PR_SRS] = rw == 2 ? 1 : 2; env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
@ -344,8 +340,7 @@ int cris_mmu_translate(struct cris_mmu_result *res,
} }
seg = vaddr >> 28; seg = vaddr >> 28;
if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG])) if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG])) {
{
uint32_t base; uint32_t base;
miss = 0; miss = 0;