mirror of
https://github.com/Motorhead1991/qemu.git
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target-arm queue:
* Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2,
PMCNTENSET_EL0 or PMCNTENCLR_EL0
* Make writes to MDCR_EL3 use PMU start/finish calls
* Let AArch32 write to SDCR.SCCD
* Rearrange cpu64.c so all the CPU initfns are together
* hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
* hw/arm/virt: fix some minor issues with generated device tree
* Fix regression where EL3 could not write to SP_EL1 if there is no EL2
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=edYy
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Merge tag 'pull-target-arm-20220930' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2,
PMCNTENSET_EL0 or PMCNTENCLR_EL0
* Make writes to MDCR_EL3 use PMU start/finish calls
* Let AArch32 write to SDCR.SCCD
* Rearrange cpu64.c so all the CPU initfns are together
* hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
* hw/arm/virt: fix some minor issues with generated device tree
* Fix regression where EL3 could not write to SP_EL1 if there is no EL2
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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 30 Sep 2022 09:33:58 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20220930' of https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
hw/arm/virt: Fix devicetree warning about the SMMU node
hw/arm/virt: Use "msi-map" devicetree property for PCI
hw/arm/virt: Fix devicetree warning about the GIC node
hw/arm/virt: Fix devicetree warning about the root node
hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
target/arm: Rearrange cpu64.c so all the CPU initfns are together
target/arm: Update SDCR_VALID_MASK to include SCCD
target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
81f12b8cdf
6 changed files with 427 additions and 372 deletions
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@ -253,6 +253,7 @@ static void create_fdt(VirtMachineState *vms)
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qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
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/* /chosen must exist for load_dtb to fill in necessary properties later */
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qemu_fdt_add_subnode(fdt, "/chosen");
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@ -487,6 +488,7 @@ static void fdt_add_its_gic_node(VirtMachineState *vms)
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qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
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"arm,gic-v3-its");
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qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
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qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
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2, vms->memmap[VIRT_GIC_ITS].base,
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2, vms->memmap[VIRT_GIC_ITS].size);
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@ -1359,8 +1361,6 @@ static void create_smmu(const VirtMachineState *vms,
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qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
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sizeof(irq_names));
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qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
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qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
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qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
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qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
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@ -1488,8 +1488,8 @@ static void create_pcie(VirtMachineState *vms)
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qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
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if (vms->msi_phandle) {
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qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
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vms->msi_phandle);
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qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
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0, vms->msi_phandle, 0, 0x10000);
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}
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qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
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@ -143,6 +143,14 @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
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77, 78, 79, 80, 81, 82, 83, 84
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};
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static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] = {
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0xFE200000, 0xFE300000
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};
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static const int usb_intr[XLNX_ZYNQMP_NUM_USB] = {
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65, 70
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};
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typedef struct XlnxZynqMPGICRegion {
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int region_index;
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uint32_t address;
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@ -428,6 +436,10 @@ static void xlnx_zynqmp_init(Object *obj)
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object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
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object_initialize_child(obj, "qspi-irq-orgate",
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&s->qspi_irq_orgate, TYPE_OR_IRQ);
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for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
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object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
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}
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}
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static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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@ -814,6 +826,30 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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object_property_add_alias(OBJECT(s), bus_name,
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OBJECT(&s->qspi), target_bus);
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
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if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma",
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OBJECT(system_memory), errp)) {
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return;
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}
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qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4);
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qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
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gic_spi[usb_intr[i]]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1,
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gic_spi[usb_intr[i] + 1]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2,
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gic_spi[usb_intr[i] + 2]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3,
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gic_spi[usb_intr[i] + 3]);
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}
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}
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static Property xlnx_zynqmp_props[] = {
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