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tcg/tci: Split out tci_args_rrrrrc

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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-01-29 21:30:04 -10:00
parent f28ca03ed5
commit 817cadd6ee
1 changed files with 19 additions and 6 deletions
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25
tcg/tci.c
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@ -223,6 +223,19 @@ static void tci_args_rrrc(const uint8_t **tb_ptr,
*c3 = tci_read_b(tb_ptr); *c3 = tci_read_b(tb_ptr);
} }
#if TCG_TARGET_REG_BITS == 32
static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
{
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*r2 = tci_read_r(tb_ptr);
*r3 = tci_read_r(tb_ptr);
*r4 = tci_read_r(tb_ptr);
*c5 = tci_read_b(tb_ptr);
}
#endif
static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
{ {
bool result = false; bool result = false;
@ -385,7 +398,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint32_t tmp32; uint32_t tmp32;
uint64_t tmp64; uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32 #if TCG_TARGET_REG_BITS == 32
uint64_t v64; TCGReg r3, r4;
uint64_t v64, T1, T2;
#endif #endif
TCGMemOpIdx oi; TCGMemOpIdx oi;
int32_t ofs; int32_t ofs;
@ -434,11 +448,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break; break;
#if TCG_TARGET_REG_BITS == 32 #if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32: case INDEX_op_setcond2_i32:
t0 = *tb_ptr++; tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition);
tmp64 = tci_read_r64(regs, &tb_ptr); T1 = tci_uint64(regs[r2], regs[r1]);
v64 = tci_read_r64(regs, &tb_ptr); T2 = tci_uint64(regs[r4], regs[r3]);
condition = *tb_ptr++; regs[r0] = tci_compare64(T1, T2, condition);
tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition));
break; break;
#elif TCG_TARGET_REG_BITS == 64 #elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64: case INDEX_op_setcond_i64: