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target/arm: Convert Logical (immediate) to decodetree

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Convert the ADD, ORR, EOR, ANDS (immediate) instructions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230512144106.3608981-10-peter.maydell@linaro.org
[PMM: rebased]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2023-05-12 15:40:55 +01:00 • committed by Peter Maydell
parent 000bcd008f
commit 8127f46a5b
2 changed files with 44 additions and 65 deletions
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15
target/arm/tcg/a64.decode
View file

@ -56,3 +56,18 @@ SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12
ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
# Logical (immediate)
&rri_log rd rn sf dbm
@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1
@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0
AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64
AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32
ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64
ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32
EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64
EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32
ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64
ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32

94
target/arm/tcg/translate-a64.c
View file

@ -4288,7 +4288,12 @@ static uint64_t bitfield_replicate(uint64_t mask, unsigned int e)
return mask; return mask;
} }
/* Simplified variant of pseudocode DecodeBitMasks() for the case where we /*
* Logical (immediate)
*/
/*
* Simplified variant of pseudocode DecodeBitMasks() for the case where we
* only require the wmask. Returns false if the imms/immr/immn are a reserved * only require the wmask. Returns false if the imms/immr/immn are a reserved
* value (ie should cause a guest UNDEF exception), and true if they are * value (ie should cause a guest UNDEF exception), and true if they are
* valid, in which case the decoded bit pattern is written to result. * valid, in which case the decoded bit pattern is written to result.
@ -4354,77 +4359,39 @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
return true; return true;
} }
/* Logical (immediate) static bool gen_rri_log(DisasContext *s, arg_rri_log *a, bool set_cc,
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0 void (*fn)(TCGv_i64, TCGv_i64, int64_t))
* +----+-----+-------------+---+------+------+------+------+
* | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
* +----+-----+-------------+---+------+------+------+------+
*/
static void disas_logic_imm(DisasContext *s, uint32_t insn)
{ {
unsigned int sf, opc, is_n, immr, imms, rn, rd;
TCGv_i64 tcg_rd, tcg_rn; TCGv_i64 tcg_rd, tcg_rn;
uint64_t wmask; uint64_t imm;
bool is_and = false;
sf = extract32(insn, 31, 1); /* Some immediate field values are reserved. */
opc = extract32(insn, 29, 2); if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1),
is_n = extract32(insn, 22, 1); extract32(a->dbm, 0, 6),
immr = extract32(insn, 16, 6); extract32(a->dbm, 6, 6))) {
imms = extract32(insn, 10, 6); return false;
rn = extract32(insn, 5, 5); }
rd = extract32(insn, 0, 5); if (!a->sf) {
imm &= 0xffffffffull;
if (!sf && is_n) {
unallocated_encoding(s);
return;
} }
if (opc == 0x3) { /* ANDS */ tcg_rd = set_cc ? cpu_reg(s, a->rd) : cpu_reg_sp(s, a->rd);
tcg_rd = cpu_reg(s, rd); tcg_rn = cpu_reg(s, a->rn);
} else {
tcg_rd = cpu_reg_sp(s, rd);
}
tcg_rn = cpu_reg(s, rn);
if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) { fn(tcg_rd, tcg_rn, imm);
/* some immediate field values are reserved */ if (set_cc) {
unallocated_encoding(s); gen_logic_CC(a->sf, tcg_rd);
return;
} }
if (!a->sf) {
if (!sf) {
wmask &= 0xffffffff;
}
switch (opc) {
case 0x3: /* ANDS */
case 0x0: /* AND */
tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask);
is_and = true;
break;
case 0x1: /* ORR */
tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask);
break;
case 0x2: /* EOR */
tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask);
break;
default:
assert(FALSE); /* must handle all above */
break;
}
if (!sf && !is_and) {
/* zero extend final result; we know we can skip this for AND
* since the immediate had the high 32 bits clear.
*/
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
} }
return true;
}
if (opc == 3) { /* ANDS */ TRANS(AND_i, gen_rri_log, a, false, tcg_gen_andi_i64)
gen_logic_CC(sf, tcg_rd); TRANS(ORR_i, gen_rri_log, a, false, tcg_gen_ori_i64)
} TRANS(EOR_i, gen_rri_log, a, false, tcg_gen_xori_i64)
} TRANS(ANDS_i, gen_rri_log, a, true, tcg_gen_andi_i64)
/* /*
* Move wide (immediate) * Move wide (immediate)
@ -4618,9 +4585,6 @@ static void disas_extract(DisasContext *s, uint32_t insn)
static void disas_data_proc_imm(DisasContext *s, uint32_t insn) static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
{ {
switch (extract32(insn, 23, 6)) { switch (extract32(insn, 23, 6)) {
case 0x24: /* Logical (immediate) */
disas_logic_imm(s, insn);
break;
case 0x25: /* Move wide (immediate) */ case 0x25: /* Move wide (immediate) */
disas_movw_imm(s, insn); disas_movw_imm(s, insn);
break; break;