mirror of
https://github.com/Motorhead1991/qemu.git
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Use DECLARE_*CHECKER* macros
Generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-13-ehabkost@redhat.com> Message-Id: <20200831210740.126168-14-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
parent
db1015e92e
commit
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791 changed files with 1987 additions and 2423 deletions
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@ -23,7 +23,8 @@
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#define TYPE_AW_A10 "allwinner-a10"
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typedef struct AwA10State AwA10State;
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#define AW_A10(obj) OBJECT_CHECK(AwA10State, (obj), TYPE_AW_A10)
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DECLARE_INSTANCE_CHECKER(AwA10State, AW_A10,
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TYPE_AW_A10)
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struct AwA10State {
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/*< private >*/
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@ -107,7 +107,8 @@ enum {
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/** Convert input object to Allwinner H3 state object */
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typedef struct AwH3State AwH3State;
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#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3)
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DECLARE_INSTANCE_CHECKER(AwH3State, AW_H3,
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TYPE_AW_H3)
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/** @} */
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@ -110,7 +110,8 @@
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#define TYPE_ARM_SSE "arm-sse"
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typedef struct ARMSSE ARMSSE;
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typedef struct ARMSSEClass ARMSSEClass;
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#define ARM_SSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARM_SSE)
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DECLARE_OBJ_CHECKERS(ARMSSE, ARMSSEClass,
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ARM_SSE, TYPE_ARM_SSE)
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/*
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* These type names are for specific IoTKit subsystems; other than
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@ -227,9 +228,5 @@ struct ARMSSEClass {
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const ARMSSEInfo *info;
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};
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#define ARM_SSE_CLASS(klass) \
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OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARM_SSE)
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#define ARM_SSE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ARMSSEClass, (obj), TYPE_ARM_SSE)
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#endif
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@ -17,7 +17,8 @@
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#define TYPE_BITBAND "ARM,bitband-memory"
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typedef struct BitBandState BitBandState;
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#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
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DECLARE_INSTANCE_CHECKER(BitBandState, BITBAND,
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TYPE_BITBAND)
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struct BitBandState {
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/*< private >*/
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@ -32,7 +33,8 @@ struct BitBandState {
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#define TYPE_ARMV7M "armv7m"
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typedef struct ARMv7MState ARMv7MState;
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#define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M)
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DECLARE_INSTANCE_CHECKER(ARMv7MState, ARMV7M,
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TYPE_ARMV7M)
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#define ARMV7M_NUM_BITBANDS 2
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@ -16,18 +16,14 @@ typedef struct AspeedMachineState AspeedMachineState;
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#define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed")
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typedef struct AspeedMachineClass AspeedMachineClass;
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#define ASPEED_MACHINE(obj) \
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OBJECT_CHECK(AspeedMachineState, (obj), TYPE_ASPEED_MACHINE)
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DECLARE_OBJ_CHECKERS(AspeedMachineState, AspeedMachineClass,
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ASPEED_MACHINE, TYPE_ASPEED_MACHINE)
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#define ASPEED_MAC0_ON (1 << 0)
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#define ASPEED_MAC1_ON (1 << 1)
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#define ASPEED_MAC2_ON (1 << 2)
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#define ASPEED_MAC3_ON (1 << 3)
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#define ASPEED_MACHINE_CLASS(klass) \
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OBJECT_CLASS_CHECK(AspeedMachineClass, (klass), TYPE_ASPEED_MACHINE)
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#define ASPEED_MACHINE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(AspeedMachineClass, (obj), TYPE_ASPEED_MACHINE)
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struct AspeedMachineClass {
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MachineClass parent_obj;
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@ -66,7 +66,8 @@ typedef struct AspeedSoCState AspeedSoCState;
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#define TYPE_ASPEED_SOC "aspeed-soc"
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typedef struct AspeedSoCClass AspeedSoCClass;
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#define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
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DECLARE_OBJ_CHECKERS(AspeedSoCState, AspeedSoCClass,
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ASPEED_SOC, TYPE_ASPEED_SOC)
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struct AspeedSoCClass {
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DeviceClass parent_class;
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@ -84,10 +85,6 @@ struct AspeedSoCClass {
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uint32_t num_cpus;
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};
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#define ASPEED_SOC_CLASS(klass) \
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OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
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#define ASPEED_SOC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
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enum {
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ASPEED_DEV_IOMEM,
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@ -33,8 +33,8 @@
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#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
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typedef struct BCM2835PeripheralState BCM2835PeripheralState;
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#define BCM2835_PERIPHERALS(obj) \
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OBJECT_CHECK(BCM2835PeripheralState, (obj), TYPE_BCM2835_PERIPHERALS)
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DECLARE_INSTANCE_CHECKER(BCM2835PeripheralState, BCM2835_PERIPHERALS,
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TYPE_BCM2835_PERIPHERALS)
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struct BCM2835PeripheralState {
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/*< private >*/
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@ -20,7 +20,8 @@
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#define TYPE_BCM283X "bcm283x"
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typedef struct BCM283XClass BCM283XClass;
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typedef struct BCM283XState BCM283XState;
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#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
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DECLARE_OBJ_CHECKERS(BCM283XState, BCM283XClass,
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BCM283X, TYPE_BCM283X)
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#define BCM283X_NCPUS 4
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@ -52,9 +53,5 @@ struct BCM283XClass {
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const BCM283XInfo *info;
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};
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#define BCM283X_CLASS(klass) \
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OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
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#define BCM283X_GET_CLASS(obj) \
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OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
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#endif /* BCM2836_H */
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@ -26,7 +26,8 @@
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#define TYPE_DIGIC "digic"
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typedef struct DigicState DigicState;
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#define DIGIC(obj) OBJECT_CHECK(DigicState, (obj), TYPE_DIGIC)
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DECLARE_INSTANCE_CHECKER(DigicState, DIGIC,
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TYPE_DIGIC)
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#define DIGIC4_NB_TIMERS 3
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@ -106,8 +106,8 @@ struct Exynos4210State {
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typedef struct Exynos4210State Exynos4210State;
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#define TYPE_EXYNOS4210_SOC "exynos4210"
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#define EXYNOS4210_SOC(obj) \
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OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
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DECLARE_INSTANCE_CHECKER(Exynos4210State, EXYNOS4210_SOC,
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TYPE_EXYNOS4210_SOC)
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void exynos4210_write_secondary(ARMCPU *cpu,
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const struct arm_boot_info *info);
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@ -36,7 +36,8 @@
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#define TYPE_FSL_IMX25 "fsl,imx25"
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typedef struct FslIMX25State FslIMX25State;
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#define FSL_IMX25(obj) OBJECT_CHECK(FslIMX25State, (obj), TYPE_FSL_IMX25)
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DECLARE_INSTANCE_CHECKER(FslIMX25State, FSL_IMX25,
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TYPE_FSL_IMX25)
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#define FSL_IMX25_NUM_UARTS 5
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#define FSL_IMX25_NUM_GPTS 4
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@ -32,7 +32,8 @@
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#define TYPE_FSL_IMX31 "fsl,imx31"
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typedef struct FslIMX31State FslIMX31State;
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#define FSL_IMX31(obj) OBJECT_CHECK(FslIMX31State, (obj), TYPE_FSL_IMX31)
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DECLARE_INSTANCE_CHECKER(FslIMX31State, FSL_IMX31,
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TYPE_FSL_IMX31)
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#define FSL_IMX31_NUM_UARTS 2
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#define FSL_IMX31_NUM_EPITS 2
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@ -38,7 +38,8 @@
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#define TYPE_FSL_IMX6 "fsl,imx6"
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typedef struct FslIMX6State FslIMX6State;
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#define FSL_IMX6(obj) OBJECT_CHECK(FslIMX6State, (obj), TYPE_FSL_IMX6)
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DECLARE_INSTANCE_CHECKER(FslIMX6State, FSL_IMX6,
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TYPE_FSL_IMX6)
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#define FSL_IMX6_NUM_CPUS 4
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#define FSL_IMX6_NUM_UARTS 5
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@ -42,7 +42,8 @@
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#define TYPE_FSL_IMX6UL "fsl,imx6ul"
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typedef struct FslIMX6ULState FslIMX6ULState;
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#define FSL_IMX6UL(obj) OBJECT_CHECK(FslIMX6ULState, (obj), TYPE_FSL_IMX6UL)
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DECLARE_INSTANCE_CHECKER(FslIMX6ULState, FSL_IMX6UL,
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TYPE_FSL_IMX6UL)
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enum FslIMX6ULConfiguration {
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FSL_IMX6UL_NUM_CPUS = 1,
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@ -43,7 +43,8 @@
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#define TYPE_FSL_IMX7 "fsl,imx7"
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typedef struct FslIMX7State FslIMX7State;
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#define FSL_IMX7(obj) OBJECT_CHECK(FslIMX7State, (obj), TYPE_FSL_IMX7)
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DECLARE_INSTANCE_CHECKER(FslIMX7State, FSL_IMX7,
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TYPE_FSL_IMX7)
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enum FslIMX7Configuration {
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FSL_IMX7_NUM_CPUS = 2,
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@ -10,10 +10,8 @@
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#define TYPE_ARM_LINUX_BOOT_IF "arm-linux-boot-if"
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typedef struct ARMLinuxBootIfClass ARMLinuxBootIfClass;
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#define ARM_LINUX_BOOT_IF_CLASS(klass) \
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OBJECT_CLASS_CHECK(ARMLinuxBootIfClass, (klass), TYPE_ARM_LINUX_BOOT_IF)
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#define ARM_LINUX_BOOT_IF_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ARMLinuxBootIfClass, (obj), TYPE_ARM_LINUX_BOOT_IF)
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DECLARE_CLASS_CHECKERS(ARMLinuxBootIfClass, ARM_LINUX_BOOT_IF,
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TYPE_ARM_LINUX_BOOT_IF)
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#define ARM_LINUX_BOOT_IF(obj) \
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INTERFACE_CHECK(ARMLinuxBootIf, (obj), TYPE_ARM_LINUX_BOOT_IF)
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@ -34,7 +34,8 @@
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#define TYPE_MSF2_SOC "msf2-soc"
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typedef struct MSF2State MSF2State;
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#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
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DECLARE_INSTANCE_CHECKER(MSF2State, MSF2_SOC,
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TYPE_MSF2_SOC)
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#define MSF2_NUM_SPIS 2
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#define MSF2_NUM_UARTS 2
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@ -21,8 +21,8 @@
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#define TYPE_NRF51_SOC "nrf51-soc"
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typedef struct NRF51State NRF51State;
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#define NRF51_SOC(obj) \
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OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC)
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DECLARE_INSTANCE_CHECKER(NRF51State, NRF51_SOC,
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TYPE_NRF51_SOC)
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#define NRF51_NUM_TIMERS 3
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@ -71,8 +71,8 @@ void omap_clk_reparent(omap_clk clk, omap_clk parent);
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/* omap_intc.c */
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#define TYPE_OMAP_INTC "common-omap-intc"
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typedef struct omap_intr_handler_s omap_intr_handler;
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#define OMAP_INTC(obj) \
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OBJECT_CHECK(omap_intr_handler, (obj), TYPE_OMAP_INTC)
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DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC,
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TYPE_OMAP_INTC)
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/*
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/* omap_i2c.c */
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#define TYPE_OMAP_I2C "omap_i2c"
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typedef struct OMAPI2CState OMAPI2CState;
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#define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C)
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DECLARE_INSTANCE_CHECKER(OMAPI2CState, OMAP_I2C,
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TYPE_OMAP_I2C)
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/* TODO: clock framework (see above) */
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/* omap_gpio.c */
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#define TYPE_OMAP1_GPIO "omap-gpio"
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#define OMAP1_GPIO(obj) \
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OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO)
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DECLARE_INSTANCE_CHECKER(struct omap_gpif_s, OMAP1_GPIO,
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TYPE_OMAP1_GPIO)
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#define TYPE_OMAP2_GPIO "omap2-gpio"
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#define OMAP2_GPIO(obj) \
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OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO)
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DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO,
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TYPE_OMAP2_GPIO)
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typedef struct omap_gpif_s omap_gpif;
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typedef struct omap2_gpif_s omap2_gpif;
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@ -89,7 +89,8 @@ void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
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/* pxa2xx_mmci.c */
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#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
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typedef struct PXA2xxMMCIState PXA2xxMMCIState;
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#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
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DECLARE_INSTANCE_CHECKER(PXA2xxMMCIState, PXA2XX_MMCI,
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TYPE_PXA2XX_MMCI)
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PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
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hwaddr base,
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@ -100,8 +101,8 @@ void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
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/* pxa2xx_pcmcia.c */
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#define TYPE_PXA2XX_PCMCIA "pxa2xx-pcmcia"
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typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
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#define PXA2XX_PCMCIA(obj) \
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OBJECT_CHECK(PXA2xxPCMCIAState, obj, TYPE_PXA2XX_PCMCIA)
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DECLARE_INSTANCE_CHECKER(PXA2xxPCMCIAState, PXA2XX_PCMCIA,
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TYPE_PXA2XX_PCMCIA)
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PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
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hwaddr base);
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@ -129,12 +130,13 @@ I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
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#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
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typedef struct PXA2xxI2SState PXA2xxI2SState;
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#define PXA2XX_I2C(obj) \
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OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
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DECLARE_INSTANCE_CHECKER(PXA2xxI2CState, PXA2XX_I2C,
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TYPE_PXA2XX_I2C)
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#define TYPE_PXA2XX_FIR "pxa2xx-fir"
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typedef struct PXA2xxFIrState PXA2xxFIrState;
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#define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR)
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DECLARE_INSTANCE_CHECKER(PXA2xxFIrState, PXA2XX_FIR,
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TYPE_PXA2XX_FIR)
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typedef struct {
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ARMCPU *cpu;
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@ -132,11 +132,8 @@ struct SMMUBaseClass {
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typedef struct SMMUBaseClass SMMUBaseClass;
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#define TYPE_ARM_SMMU "arm-smmu"
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#define ARM_SMMU(obj) OBJECT_CHECK(SMMUState, (obj), TYPE_ARM_SMMU)
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#define ARM_SMMU_CLASS(klass) \
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OBJECT_CLASS_CHECK(SMMUBaseClass, (klass), TYPE_ARM_SMMU)
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#define ARM_SMMU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(SMMUBaseClass, (obj), TYPE_ARM_SMMU)
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DECLARE_OBJ_CHECKERS(SMMUState, SMMUBaseClass,
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ARM_SMMU, TYPE_ARM_SMMU)
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/* Return the SMMUPciBus handle associated to a PCI bus number */
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SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num);
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@ -83,10 +83,7 @@ struct SMMUv3Class {
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typedef struct SMMUv3Class SMMUv3Class;
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#define TYPE_ARM_SMMUV3 "arm-smmuv3"
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#define ARM_SMMUV3(obj) OBJECT_CHECK(SMMUv3State, (obj), TYPE_ARM_SMMUV3)
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#define ARM_SMMUV3_CLASS(klass) \
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OBJECT_CLASS_CHECK(SMMUv3Class, (klass), TYPE_ARM_SMMUV3)
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#define ARM_SMMUV3_GET_CLASS(obj) \
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OBJECT_GET_CLASS(SMMUv3Class, (obj), TYPE_ARM_SMMUV3)
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DECLARE_OBJ_CHECKERS(SMMUv3State, SMMUv3Class,
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ARM_SMMUV3, TYPE_ARM_SMMUV3)
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#endif
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@ -36,8 +36,8 @@
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#define TYPE_STM32F205_SOC "stm32f205-soc"
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typedef struct STM32F205State STM32F205State;
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#define STM32F205_SOC(obj) \
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OBJECT_CHECK(STM32F205State, (obj), TYPE_STM32F205_SOC)
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DECLARE_INSTANCE_CHECKER(STM32F205State, STM32F205_SOC,
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TYPE_STM32F205_SOC)
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#define STM_NUM_USARTS 6
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#define STM_NUM_TIMERS 4
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|
@ -37,8 +37,8 @@
|
|||
|
||||
#define TYPE_STM32F405_SOC "stm32f405-soc"
|
||||
typedef struct STM32F405State STM32F405State;
|
||||
#define STM32F405_SOC(obj) \
|
||||
OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC)
|
||||
DECLARE_INSTANCE_CHECKER(STM32F405State, STM32F405_SOC,
|
||||
TYPE_STM32F405_SOC)
|
||||
|
||||
#define STM_NUM_USARTS 7
|
||||
#define STM_NUM_TIMERS 4
|
||||
|
|
|
@ -170,12 +170,8 @@ typedef struct VirtMachineState VirtMachineState;
|
|||
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
|
||||
|
||||
#define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
|
||||
#define VIRT_MACHINE(obj) \
|
||||
OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
|
||||
#define VIRT_MACHINE_GET_CLASS(obj) \
|
||||
OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
|
||||
#define VIRT_MACHINE_CLASS(klass) \
|
||||
OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
|
||||
DECLARE_OBJ_CHECKERS(VirtMachineState, VirtMachineClass,
|
||||
VIRT_MACHINE, TYPE_VIRT_MACHINE)
|
||||
|
||||
void virt_acpi_setup(VirtMachineState *vms);
|
||||
bool virt_is_acpi_enabled(VirtMachineState *vms);
|
||||
|
|
|
@ -24,7 +24,8 @@
|
|||
|
||||
#define TYPE_XLNX_VERSAL "xlnx-versal"
|
||||
typedef struct Versal Versal;
|
||||
#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
|
||||
DECLARE_INSTANCE_CHECKER(Versal, XLNX_VERSAL,
|
||||
TYPE_XLNX_VERSAL)
|
||||
|
||||
#define XLNX_VERSAL_NR_ACPUS 2
|
||||
#define XLNX_VERSAL_NR_UARTS 2
|
||||
|
|
|
@ -36,8 +36,8 @@
|
|||
|
||||
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
|
||||
typedef struct XlnxZynqMPState XlnxZynqMPState;
|
||||
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
|
||||
TYPE_XLNX_ZYNQMP)
|
||||
DECLARE_INSTANCE_CHECKER(XlnxZynqMPState, XLNX_ZYNQMP,
|
||||
TYPE_XLNX_ZYNQMP)
|
||||
|
||||
#define XLNX_ZYNQMP_NUM_APU_CPUS 4
|
||||
#define XLNX_ZYNQMP_NUM_RPU_CPUS 2
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue