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https://github.com/Motorhead1991/qemu.git
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sh775x interrupt controller by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3327 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog
parent
30d6eaca96
commit
80f515e636
6 changed files with 631 additions and 91 deletions
223
hw/sh7750.c
223
hw/sh7750.c
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@ -1,6 +1,7 @@
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/*
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* SH7750 device
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*
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* Copyright (c) 2007 Magnus Damm
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* Copyright (c) 2005 Samuel Tardieu
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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@ -26,6 +27,7 @@
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#include "vl.h"
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#include "sh7750_regs.h"
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#include "sh7750_regnames.h"
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#include "sh_intc.h"
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#define NB_DEVICES 4
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@ -53,15 +55,10 @@ typedef struct SH7750State {
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sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
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uint16_t icr;
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uint16_t ipra;
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uint16_t iprb;
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uint16_t iprc;
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uint16_t iprd;
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uint32_t intpri00;
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uint32_t intmsk00;
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/* Cache */
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uint32_t ccr;
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struct intc_desc intc;
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} SH7750State;
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@ -219,14 +216,6 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
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return portb_lines(s);
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case 0x1fd00000:
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return s->icr;
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case 0x1fd00004:
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return s->ipra;
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case 0x1fd00008:
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return s->iprb;
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case 0x1fd0000c:
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return s->iprc;
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case 0x1fd00010:
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return s->iprd;
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default:
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error_access("word read", addr);
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assert(0);
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@ -262,14 +251,6 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
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return 0x00110000; /* Minimum caches */
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case 0x1f000044: /* Processor version PRR */
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return 0x00000100; /* SH7750R */
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case 0x1e080000:
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return s->intpri00;
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case 0x1e080020:
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return 0;
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case 0x1e080040:
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return s->intmsk00;
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case 0x1e080060:
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return 0;
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default:
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error_access("long read", addr);
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assert(0);
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@ -331,18 +312,6 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
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case 0x1fd00000:
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s->icr = mem_value;
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return;
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case 0x1fd00004:
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s->ipra = mem_value;
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return;
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case 0x1fd00008:
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s->iprb = mem_value;
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return;
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case 0x1fd0000c:
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s->iprc = mem_value;
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return;
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case 0x1fd00010:
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s->iprd = mem_value;
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return;
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default:
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error_access("word write", addr);
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assert(0);
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@ -407,16 +376,6 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
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case SH7750_CCR_A7:
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s->ccr = mem_value;
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return;
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case 0x1e080000:
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s->intpri00 = mem_value;
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return;
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case 0x1e080020:
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return;
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case 0x1e080040:
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s->intmsk00 = mem_value;
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return;
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case 0x1e080060:
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return;
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default:
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error_access("long write", addr);
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assert(0);
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@ -435,10 +394,144 @@ static CPUWriteMemoryFunc *sh7750_mem_write[] = {
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sh7750_mem_writel
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};
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/* sh775x interrupt controller tables for sh_intc.c
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* stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
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*/
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
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HUDI, GPIOI,
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DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
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DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
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DMAC_DMAE,
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PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
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PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
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TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
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RTC_ATI, RTC_PRI, RTC_CUI,
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SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
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SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
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WDT,
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REF_RCMI, REF_ROVI,
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/* interrupt groups */
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DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
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NR_SOURCES,
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};
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static struct intc_vect vectors[] = {
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INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
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INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
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INTC_VECT(RTC_CUI, 0x4c0),
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INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
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INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
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INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
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INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
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INTC_VECT(WDT, 0x560),
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INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
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};
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static struct intc_group groups[] = {
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INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
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INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
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INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
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INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
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INTC_GROUP(REF, REF_RCMI, REF_ROVI),
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};
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static struct intc_prio_reg prio_registers[] = {
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{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
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{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
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{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
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{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
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{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
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TMU4, TMU3,
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PCIC1, PCIC0_PCISERR } },
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};
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/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
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static struct intc_vect vectors_dma4[] = {
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INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
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INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
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INTC_VECT(DMAC_DMAE, 0x6c0),
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};
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static struct intc_group groups_dma4[] = {
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INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
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DMAC_DMTE3, DMAC_DMAE),
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};
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/* SH7750R and SH7751R both have 8-channel DMA controllers */
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static struct intc_vect vectors_dma8[] = {
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INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
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INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
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INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
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INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
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INTC_VECT(DMAC_DMAE, 0x6c0),
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};
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static struct intc_group groups_dma8[] = {
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INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
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DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
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DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
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};
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/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
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static struct intc_vect vectors_tmu34[] = {
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INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
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};
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static struct intc_mask_reg mask_registers[] = {
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{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, TMU4, TMU3,
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PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
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PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
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PCIC1_PCIDMA3, PCIC0_PCISERR } },
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};
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/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
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static struct intc_vect vectors_irlm[] = {
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INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
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INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
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};
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/* SH7751 and SH7751R both have PCI */
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static struct intc_vect vectors_pci[] = {
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INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
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INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
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INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
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INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
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};
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static struct intc_group groups_pci[] = {
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INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
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PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
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};
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#define SH_CPU_SH7750 (1 << 0)
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#define SH_CPU_SH7750S (1 << 1)
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#define SH_CPU_SH7750R (1 << 2)
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#define SH_CPU_SH7751 (1 << 3)
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#define SH_CPU_SH7751R (1 << 4)
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#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
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#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
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SH7750State *sh7750_init(CPUSH4State * cpu)
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{
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SH7750State *s;
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int sh7750_io_memory;
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int cpu_model = SH_CPU_SH7751R; /* for now */
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s = qemu_mallocz(sizeof(SH7750State));
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s->cpu = cpu;
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@ -448,6 +541,14 @@ SH7750State *sh7750_init(CPUSH4State * cpu)
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sh7750_mem_write, s);
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cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);
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sh_intc_init(&s->intc, NR_SOURCES,
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_INTC_ARRAY(mask_registers),
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_INTC_ARRAY(prio_registers));
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sh_intc_register_sources(&s->intc,
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_INTC_ARRAY(vectors),
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_INTC_ARRAY(groups));
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sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0]);
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sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
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s->periph_freq, serial_hds[1]);
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@ -455,6 +556,38 @@ SH7750State *sh7750_init(CPUSH4State * cpu)
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tmu012_init(0x1fd80000,
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TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
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s->periph_freq);
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tmu012_init(0x1e100000, 0, s->periph_freq);
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if (cpu_model & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
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sh_intc_register_sources(&s->intc,
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_INTC_ARRAY(vectors_dma4),
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_INTC_ARRAY(groups_dma4));
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}
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if (cpu_model & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
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sh_intc_register_sources(&s->intc,
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_INTC_ARRAY(vectors_dma8),
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_INTC_ARRAY(groups_dma8));
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}
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if (cpu_model & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
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sh_intc_register_sources(&s->intc,
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_INTC_ARRAY(vectors_tmu34),
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_INTC_ARRAY(NULL));
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tmu012_init(0x1e100000, 0, s->periph_freq);
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}
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if (cpu_model & (SH_CPU_SH7751_ALL)) {
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sh_intc_register_sources(&s->intc,
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_INTC_ARRAY(vectors_pci),
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_INTC_ARRAY(groups_pci));
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}
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if (cpu_model & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
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sh_intc_register_sources(&s->intc,
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_INTC_ARRAY(vectors_irlm),
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_INTC_ARRAY(NULL));
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}
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return s;
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}
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