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target-mips: add MSA I5 format instruction

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add MSA I5 format instructions

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Yongbok Kim 2014-11-01 05:28:44 +00:00 • committed by Leon Alrae
parent 4c7895465e
commit 80e7159184
3 changed files with 232 additions and 0 deletions
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77
target-mips/translate.c
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@ -17392,6 +17392,79 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(ti8);
}
static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
{
#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
uint8_t df = (ctx->opcode >> 21) & 0x3;
int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
uint8_t u5 = (ctx->opcode >> 16) & 0x1f;
uint8_t ws = (ctx->opcode >> 11) & 0x1f;
uint8_t wd = (ctx->opcode >> 6) & 0x1f;
TCGv_i32 tdf = tcg_const_i32(df);
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
TCGv_i32 timm = tcg_temp_new_i32();
tcg_gen_movi_i32(timm, u5);
switch (MASK_MSA_I5(ctx->opcode)) {
case OPC_ADDVI_df:
gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm);
break;
case OPC_SUBVI_df:
gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm);
break;
case OPC_MAXI_S_df:
tcg_gen_movi_i32(timm, s5);
gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm);
break;
case OPC_MAXI_U_df:
gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm);
break;
case OPC_MINI_S_df:
tcg_gen_movi_i32(timm, s5);
gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm);
break;
case OPC_MINI_U_df:
gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm);
break;
case OPC_CEQI_df:
tcg_gen_movi_i32(timm, s5);
gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm);
break;
case OPC_CLTI_S_df:
tcg_gen_movi_i32(timm, s5);
gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm);
break;
case OPC_CLTI_U_df:
gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm);
break;
case OPC_CLEI_S_df:
tcg_gen_movi_i32(timm, s5);
gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm);
break;
case OPC_CLEI_U_df:
gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
break;
case OPC_LDI_df:
{
int32_t s10 = sextract32(ctx->opcode, 11, 10);
tcg_gen_movi_i32(timm, s10);
gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
}
break;
default:
MIPS_INVAL("MSA instruction");
generate_exception(ctx, EXCP_RI);
break;
}
tcg_temp_free_i32(tdf);
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
tcg_temp_free_i32(timm);
}
static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;
@ -17404,6 +17477,10 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
case OPC_MSA_I8_02:
gen_msa_i8(env, ctx);
break;
case OPC_MSA_I5_06:
case OPC_MSA_I5_07:
gen_msa_i5(env, ctx);
break;
default:
MIPS_INVAL("MSA instruction");
generate_exception(ctx, EXCP_RI);