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hw/cpu: Constify all Property

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-13 15:25:18 +00:00
parent f5ca2d6233
commit 804467e148
5 changed files with 5 additions and 5 deletions
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2
hw/cpu/a15mpcore.c
View file

@ -144,7 +144,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
} }
} }
static Property a15mp_priv_properties[] = { static const Property a15mp_priv_properties[] = {
DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
/* The Cortex-A15MP may have anything from 0 to 224 external interrupt /* The Cortex-A15MP may have anything from 0 to 224 external interrupt
* IRQ lines (with another 32 internal). We default to 128+32, which * IRQ lines (with another 32 internal). We default to 128+32, which

2
hw/cpu/a9mpcore.c
View file

@ -158,7 +158,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
} }
} }
static Property a9mp_priv_properties[] = { static const Property a9mp_priv_properties[] = {
DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
/* The Cortex-A9MP may have anything from 0 to 224 external interrupt /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
* IRQ lines (with another 32 internal). We default to 64+32, which * IRQ lines (with another 32 internal). We default to 64+32, which

2
hw/cpu/arm11mpcore.c
View file

@ -131,7 +131,7 @@ static void mpcore_priv_initfn(Object *obj)
object_initialize_child(obj, "wdtimer", &s->wdtimer, TYPE_ARM_MPTIMER); object_initialize_child(obj, "wdtimer", &s->wdtimer, TYPE_ARM_MPTIMER);
} }
static Property mpcore_priv_properties[] = { static const Property mpcore_priv_properties[] = {
DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
/* The ARM11 MPCORE TRM says the on-chip controller may have /* The ARM11 MPCORE TRM says the on-chip controller may have
* anything from 0 to 224 external interrupt IRQ lines (with another * anything from 0 to 224 external interrupt IRQ lines (with another

2
hw/cpu/cluster.c
View file

@ -25,7 +25,7 @@
#include "hw/qdev-properties.h" #include "hw/qdev-properties.h"
#include "qapi/error.h" #include "qapi/error.h"
static Property cpu_cluster_properties[] = { static const Property cpu_cluster_properties[] = {
DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0),
DEFINE_PROP_END_OF_LIST() DEFINE_PROP_END_OF_LIST()
}; };

2
hw/cpu/realview_mpcore.c
View file

@ -108,7 +108,7 @@ static void mpcore_rirq_init(Object *obj)
} }
} }
static Property mpcore_rirq_properties[] = { static const Property mpcore_rirq_properties[] = {
DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };