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target-arm queue:
* raspi: add model of cprman clock manager * sbsa-ref: add an SBSA generic watchdog device * arm/trace: Fix hex printing * raspi: Add models of Pi 3 model A+, Pi Zero and Pi A+ * hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitly * Nuvoton NPCM7xx: Add USB, RNG, GPIO and watchdog support * hw/arm: fix min_cpus for xlnx-versal-virt platform * hw/arm/highbank: Silence warnings about missing fallthrough statements * linux-user: Support Aarch64 BTI * Armv7M systick: fix corner case bugs by rewriting to use ptimer -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAl+YBA4ZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3rWRD/9hqjzL4d7xKcFQdQdRXsxv 7zX82arHdxg9pNvusie/tuhX0PLswQ8TPEHEBVQvngxF7y/HqLBFuZAQvFf4ou6R 9+myTXE2RuWHOYKlrr/M6p4csABXNMm7PiA3VMeKcTEh4DoamLyBz6j1X4obPiA+ tLaRw4azzYAZnHoCaF6BX+4uf4bQZoqAtAS4IodJAAbDXJStl0VUFoS34MPhgW6/ dwGF8DbQJVYRqa7xEXck4Yx7dkx13I66+iYUf9kCyoCkdyz1sIq58fbKhXQP4lqN I3e5XGBVJfeku7w/TGOpsw8OCyTng0z636iglfLVOrsj5N03fT8j72ehY7jJsN9f CgHvQ1JAX1DvA/v23oxs3WccwAOfJJsOERtf9QxyMbTR1czCeIY1LYMnkOFtyL87 6IQpwM0WF1z4lja0dmrvhKJWjqn+kVI2cDtxrprsulCHi+pcIdJMq8vJDfxjpqqe SnDXVSAn8KjBrClaJRqHfbi+5ggsTwsLpBtEToQ4AOR342XVRfEY8IfTLb1D2+6q z99BFiyJtZ6iiJq5jgGMhppN6tEuHFK7Vr6IwhGDgFTchWb6by+K3i8/VzrbWVk9 O+KEeO92dg6jVd+6FyXOPnJ3DcUXEp6EVUVrKBBUC+LTU8Lf1MCgeprjSi87UHIX xQg635uOQU3gxkqxCaE0XA== =OFlu -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201027-1' into staging target-arm queue: * raspi: add model of cprman clock manager * sbsa-ref: add an SBSA generic watchdog device * arm/trace: Fix hex printing * raspi: Add models of Pi 3 model A+, Pi Zero and Pi A+ * hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitly * Nuvoton NPCM7xx: Add USB, RNG, GPIO and watchdog support * hw/arm: fix min_cpus for xlnx-versal-virt platform * hw/arm/highbank: Silence warnings about missing fallthrough statements * linux-user: Support Aarch64 BTI * Armv7M systick: fix corner case bugs by rewriting to use ptimer # gpg: Signature made Tue 27 Oct 2020 11:27:10 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20201027-1: (48 commits) hw/timer/armv7m_systick: Rewrite to use ptimers hw/core/ptimer: Support ptimer being disabled by timer callback hw/arm/sbsa-ref: add SBSA watchdog device hw/watchdog: Implement SBSA watchdog device hw/arm/bcm2835_peripherals: connect the UART clock hw/char/pl011: add a clock input hw/misc/bcm2835_cprman: add sane reset values to the registers hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer hw/misc/bcm2835_cprman: implement clock mux behaviour hw/misc/bcm2835_cprman: add a clock mux skeleton implementation hw/misc/bcm2835_cprman: implement PLL channels behaviour hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation hw/misc/bcm2835_cprman: implement PLLs behaviour hw/misc/bcm2835_cprman: add a PLL skeleton implementation hw/arm/raspi: add a skeleton implementation of the CPRMAN hw/arm/raspi: fix CPRMAN base address hw/core/clock: trace clock values in Hz instead of ns hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro arm/trace: Fix hex printing hw/arm/raspi: Add the Raspberry Pi 3 model A+ ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
802427bcda
64 changed files with 5461 additions and 279 deletions
210
include/hw/misc/bcm2835_cprman.h
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210
include/hw/misc/bcm2835_cprman.h
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@ -0,0 +1,210 @@
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/*
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* BCM2835 CPRMAN clock manager
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*
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* Copyright (c) 2020 Luc Michel <luc@lmichel.fr>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_MISC_CPRMAN_H
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#define HW_MISC_CPRMAN_H
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#include "hw/sysbus.h"
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#include "hw/qdev-clock.h"
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#define TYPE_BCM2835_CPRMAN "bcm2835-cprman"
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typedef struct BCM2835CprmanState BCM2835CprmanState;
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DECLARE_INSTANCE_CHECKER(BCM2835CprmanState, CPRMAN,
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TYPE_BCM2835_CPRMAN)
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#define CPRMAN_NUM_REGS (0x2000 / sizeof(uint32_t))
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typedef enum CprmanPll {
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CPRMAN_PLLA = 0,
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CPRMAN_PLLC,
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CPRMAN_PLLD,
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CPRMAN_PLLH,
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CPRMAN_PLLB,
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CPRMAN_NUM_PLL
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} CprmanPll;
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typedef enum CprmanPllChannel {
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CPRMAN_PLLA_CHANNEL_DSI0 = 0,
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CPRMAN_PLLA_CHANNEL_CORE,
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CPRMAN_PLLA_CHANNEL_PER,
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CPRMAN_PLLA_CHANNEL_CCP2,
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CPRMAN_PLLC_CHANNEL_CORE2,
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CPRMAN_PLLC_CHANNEL_CORE1,
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CPRMAN_PLLC_CHANNEL_PER,
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CPRMAN_PLLC_CHANNEL_CORE0,
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CPRMAN_PLLD_CHANNEL_DSI0,
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CPRMAN_PLLD_CHANNEL_CORE,
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CPRMAN_PLLD_CHANNEL_PER,
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CPRMAN_PLLD_CHANNEL_DSI1,
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CPRMAN_PLLH_CHANNEL_AUX,
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CPRMAN_PLLH_CHANNEL_RCAL,
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CPRMAN_PLLH_CHANNEL_PIX,
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CPRMAN_PLLB_CHANNEL_ARM,
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CPRMAN_NUM_PLL_CHANNEL,
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/* Special values used when connecting clock sources to clocks */
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CPRMAN_CLOCK_SRC_NORMAL = -1,
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CPRMAN_CLOCK_SRC_FORCE_GROUND = -2,
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CPRMAN_CLOCK_SRC_DSI0HSCK = -3,
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} CprmanPllChannel;
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typedef enum CprmanClockMux {
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CPRMAN_CLOCK_GNRIC,
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CPRMAN_CLOCK_VPU,
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CPRMAN_CLOCK_SYS,
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CPRMAN_CLOCK_PERIA,
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CPRMAN_CLOCK_PERII,
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CPRMAN_CLOCK_H264,
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CPRMAN_CLOCK_ISP,
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CPRMAN_CLOCK_V3D,
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CPRMAN_CLOCK_CAM0,
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CPRMAN_CLOCK_CAM1,
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CPRMAN_CLOCK_CCP2,
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CPRMAN_CLOCK_DSI0E,
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CPRMAN_CLOCK_DSI0P,
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CPRMAN_CLOCK_DPI,
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CPRMAN_CLOCK_GP0,
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CPRMAN_CLOCK_GP1,
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CPRMAN_CLOCK_GP2,
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CPRMAN_CLOCK_HSM,
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CPRMAN_CLOCK_OTP,
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CPRMAN_CLOCK_PCM,
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CPRMAN_CLOCK_PWM,
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CPRMAN_CLOCK_SLIM,
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CPRMAN_CLOCK_SMI,
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CPRMAN_CLOCK_TEC,
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CPRMAN_CLOCK_TD0,
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CPRMAN_CLOCK_TD1,
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CPRMAN_CLOCK_TSENS,
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CPRMAN_CLOCK_TIMER,
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CPRMAN_CLOCK_UART,
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CPRMAN_CLOCK_VEC,
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CPRMAN_CLOCK_PULSE,
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CPRMAN_CLOCK_SDC,
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CPRMAN_CLOCK_ARM,
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CPRMAN_CLOCK_AVEO,
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CPRMAN_CLOCK_EMMC,
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CPRMAN_CLOCK_EMMC2,
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CPRMAN_NUM_CLOCK_MUX
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} CprmanClockMux;
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typedef enum CprmanClockMuxSource {
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CPRMAN_CLOCK_SRC_GND = 0,
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CPRMAN_CLOCK_SRC_XOSC,
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CPRMAN_CLOCK_SRC_TD0,
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CPRMAN_CLOCK_SRC_TD1,
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CPRMAN_CLOCK_SRC_PLLA,
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CPRMAN_CLOCK_SRC_PLLC,
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CPRMAN_CLOCK_SRC_PLLD,
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CPRMAN_CLOCK_SRC_PLLH,
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CPRMAN_CLOCK_SRC_PLLC_CORE1,
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CPRMAN_CLOCK_SRC_PLLC_CORE2,
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CPRMAN_NUM_CLOCK_MUX_SRC
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} CprmanClockMuxSource;
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typedef struct CprmanPllState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CprmanPll id;
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uint32_t *reg_cm;
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uint32_t *reg_a2w_ctrl;
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uint32_t *reg_a2w_ana; /* ANA[0] .. ANA[3] */
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uint32_t prediv_mask; /* prediv bit in ana[1] */
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uint32_t *reg_a2w_frac;
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Clock *xosc_in;
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Clock *out;
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} CprmanPllState;
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typedef struct CprmanPllChannelState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CprmanPllChannel id;
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CprmanPll parent;
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uint32_t *reg_cm;
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uint32_t hold_mask;
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uint32_t load_mask;
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uint32_t *reg_a2w_ctrl;
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int fixed_divider;
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Clock *pll_in;
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Clock *out;
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} CprmanPllChannelState;
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typedef struct CprmanClockMuxState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CprmanClockMux id;
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uint32_t *reg_ctl;
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uint32_t *reg_div;
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int int_bits;
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int frac_bits;
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Clock *srcs[CPRMAN_NUM_CLOCK_MUX_SRC];
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Clock *out;
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/*
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* Used by clock srcs update callback to retrieve both the clock and the
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* source number.
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*/
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struct CprmanClockMuxState *backref[CPRMAN_NUM_CLOCK_MUX_SRC];
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} CprmanClockMuxState;
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typedef struct CprmanDsi0HsckMuxState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CprmanClockMux id;
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uint32_t *reg_cm;
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Clock *plla_in;
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Clock *plld_in;
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Clock *out;
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} CprmanDsi0HsckMuxState;
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struct BCM2835CprmanState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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CprmanPllState plls[CPRMAN_NUM_PLL];
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CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL];
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CprmanClockMuxState clock_muxes[CPRMAN_NUM_CLOCK_MUX];
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CprmanDsi0HsckMuxState dsi0hsck_mux;
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uint32_t regs[CPRMAN_NUM_REGS];
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uint32_t xosc_freq;
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Clock *xosc;
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Clock *gnd;
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};
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#endif
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1019
include/hw/misc/bcm2835_cprman_internals.h
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1019
include/hw/misc/bcm2835_cprman_internals.h
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File diff suppressed because it is too large
Load diff
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*/
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#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
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#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
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typedef struct NPCM7xxCLKState {
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SysBusDevice parent;
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34
include/hw/misc/npcm7xx_rng.h
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include/hw/misc/npcm7xx_rng.h
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/*
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* Nuvoton NPCM7xx Random Number Generator.
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM7XX_RNG_H
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#define NPCM7XX_RNG_H
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#include "hw/sysbus.h"
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typedef struct NPCM7xxRNGState {
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SysBusDevice parent;
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MemoryRegion iomem;
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uint8_t rngcs;
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uint8_t rngd;
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uint8_t rngmode;
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} NPCM7xxRNGState;
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#define TYPE_NPCM7XX_RNG "npcm7xx-rng"
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#define NPCM7XX_RNG(obj) OBJECT_CHECK(NPCM7xxRNGState, (obj), TYPE_NPCM7XX_RNG)
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#endif /* NPCM7XX_RNG_H */
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