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target-arm queue:

Browse source 
* raspi: add model of cprman clock manager
  * sbsa-ref: add an SBSA generic watchdog device
  * arm/trace: Fix hex printing
  * raspi: Add models of Pi 3 model A+, Pi Zero and Pi A+
  * hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitly
  * Nuvoton NPCM7xx: Add USB, RNG, GPIO and watchdog support
  * hw/arm: fix min_cpus for xlnx-versal-virt platform
  * hw/arm/highbank: Silence warnings about missing fallthrough statements
  * linux-user: Support Aarch64 BTI
  * Armv7M systick: fix corner case bugs by rewriting to use ptimer
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201027-1' into staging

target-arm queue:
 * raspi: add model of cprman clock manager
 * sbsa-ref: add an SBSA generic watchdog device
 * arm/trace: Fix hex printing
 * raspi: Add models of Pi 3 model A+, Pi Zero and Pi A+
 * hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitly
 * Nuvoton NPCM7xx: Add USB, RNG, GPIO and watchdog support
 * hw/arm: fix min_cpus for xlnx-versal-virt platform
 * hw/arm/highbank: Silence warnings about missing fallthrough statements
 * linux-user: Support Aarch64 BTI
 * Armv7M systick: fix corner case bugs by rewriting to use ptimer

# gpg: Signature made Tue 27 Oct 2020 11:27:10 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20201027-1: (48 commits)
  hw/timer/armv7m_systick: Rewrite to use ptimers
  hw/core/ptimer: Support ptimer being disabled by timer callback
  hw/arm/sbsa-ref: add SBSA watchdog device
  hw/watchdog: Implement SBSA watchdog device
  hw/arm/bcm2835_peripherals: connect the UART clock
  hw/char/pl011: add a clock input
  hw/misc/bcm2835_cprman: add sane reset values to the registers
  hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer
  hw/misc/bcm2835_cprman: implement clock mux behaviour
  hw/misc/bcm2835_cprman: add a clock mux skeleton implementation
  hw/misc/bcm2835_cprman: implement PLL channels behaviour
  hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation
  hw/misc/bcm2835_cprman: implement PLLs behaviour
  hw/misc/bcm2835_cprman: add a PLL skeleton implementation
  hw/arm/raspi: add a skeleton implementation of the CPRMAN
  hw/arm/raspi: fix CPRMAN base address
  hw/core/clock: trace clock values in Hz instead of ns
  hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro
  arm/trace: Fix hex printing
  hw/arm/raspi: Add the Raspberry Pi 3 model A+
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-10-29 11:40:04 +00:00
commit 802427bcda
64 changed files with 5461 additions and 279 deletions
Download patch file Download diff file Expand all files Collapse all files

22
include/elf.h
View file

@ -26,9 +26,13 @@ typedef int64_t Elf64_Sxword;
#define PT_NOTE 4
#define PT_SHLIB 5
#define PT_PHDR 6
#define PT_LOOS 0x60000000
#define PT_HIOS 0x6fffffff
#define PT_LOPROC 0x70000000
#define PT_HIPROC 0x7fffffff
#define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
#define PT_MIPS_REGINFO 0x70000000
#define PT_MIPS_RTPROC 0x70000001
#define PT_MIPS_OPTIONS 0x70000002
@ -1659,6 +1663,24 @@ typedef struct elf64_shdr {
#define NT_ARM_SYSTEM_CALL 0x404 /* ARM system call number */
#define NT_ARM_SVE 0x405 /* ARM Scalable Vector Extension regs */
/* Defined note types for GNU systems. */
#define NT_GNU_PROPERTY_TYPE_0 5 /* Program property */
/* Values used in GNU .note.gnu.property notes (NT_GNU_PROPERTY_TYPE_0). */
#define GNU_PROPERTY_STACK_SIZE 1
#define GNU_PROPERTY_NO_COPY_ON_PROTECTED 2
#define GNU_PROPERTY_LOPROC 0xc0000000
#define GNU_PROPERTY_HIPROC 0xdfffffff
#define GNU_PROPERTY_LOUSER 0xe0000000
#define GNU_PROPERTY_HIUSER 0xffffffff
#define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
#define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1u << 0)
#define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1u << 1)
/*
* Physical entry point into the kernel.
*

2
include/exec/cpu-all.h
View file

@ -274,6 +274,8 @@ extern intptr_t qemu_host_page_mask;
/* FIXME: Code that sets/uses this is broken and needs to go away. */
#define PAGE_RESERVED 0x0020
#endif
/* Target-specific bits that will be used via page_get_flags(). */
#define PAGE_TARGET_1 0x0080
#if defined(CONFIG_USER_ONLY)
void page_dump(FILE *f);

5
include/hw/arm/bcm2835_peripherals.h
View file

@ -23,6 +23,7 @@
#include "hw/misc/bcm2835_mbox.h"
#include "hw/misc/bcm2835_mphi.h"
#include "hw/misc/bcm2835_thermal.h"
#include "hw/misc/bcm2835_cprman.h"
#include "hw/sd/sdhci.h"
#include "hw/sd/bcm2835_sdhost.h"
#include "hw/gpio/bcm2835_gpio.h"
@ -47,8 +48,8 @@ struct BCM2835PeripheralState {
BCM2835MphiState mphi;
UnimplementedDeviceState txp;
UnimplementedDeviceState armtmr;
UnimplementedDeviceState cprman;
UnimplementedDeviceState a2w;
UnimplementedDeviceState powermgt;
BCM2835CprmanState cprman;
PL011State uart0;
BCM2835AuxState aux;
BCM2835FBState fb;

9
include/hw/arm/bcm2836.h
View file

@ -26,6 +26,7 @@ OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
* them, code using these devices should always handle them via the
* BCM283x base class, so they have no BCM2836(obj) etc macros.
*/
#define TYPE_BCM2835 "bcm2835"
#define TYPE_BCM2836 "bcm2836"
#define TYPE_BCM2837 "bcm2837"
@ -43,12 +44,4 @@ struct BCM283XState {
BCM2835PeripheralState peripherals;
};
typedef struct BCM283XInfo BCM283XInfo;
struct BCM283XClass {
DeviceClass parent_class;
const BCM283XInfo *info;
};
#endif /* BCM2836_H */

8
include/hw/arm/npcm7xx.h
View file

@ -18,12 +18,16 @@
#include "hw/boards.h"
#include "hw/cpu/a9mpcore.h"
#include "hw/gpio/npcm7xx_gpio.h"
#include "hw/mem/npcm7xx_mc.h"
#include "hw/misc/npcm7xx_clk.h"
#include "hw/misc/npcm7xx_gcr.h"
#include "hw/misc/npcm7xx_rng.h"
#include "hw/nvram/npcm7xx_otp.h"
#include "hw/timer/npcm7xx_timer.h"
#include "hw/ssi/npcm7xx_fiu.h"
#include "hw/usb/hcd-ehci.h"
#include "hw/usb/hcd-ohci.h"
#include "target/arm/cpu.h"
#define NPCM7XX_MAX_NUM_CPUS (2)
@ -75,6 +79,10 @@ typedef struct NPCM7xxState {
NPCM7xxOTPState key_storage;
NPCM7xxOTPState fuse_array;
NPCM7xxMCState mc;
NPCM7xxRNGState rng;
NPCM7xxGPIOState gpio[8];
EHCISysBusState ehci;
OHCISysBusState ohci;
NPCM7xxFIUState fiu[2];
} NPCM7xxState;

5
include/hw/arm/raspi_platform.h
View file

@ -45,9 +45,8 @@
#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */
#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
* Doorbells & Mailboxes */
#define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */
#define CM_OFFSET 0x101000 /* Clock Management */
#define A2W_OFFSET 0x102000 /* Reset controller */
#define PM_OFFSET 0x100000 /* Power Management */
#define CPRMAN_OFFSET 0x101000 /* Clock Management */
#define AVS_OFFSET 0x103000 /* Audio Video Standard */
#define RNG_OFFSET 0x104000
#define GPIO_OFFSET 0x200000

1
include/hw/char/pl011.h
View file

@ -49,6 +49,7 @@ struct PL011State {
int read_trigger;
CharBackend chr;
qemu_irq irq[6];
Clock *clk;
const unsigned char *id;
};

5
include/hw/clock.h
View file

@ -81,6 +81,11 @@ extern const VMStateDescription vmstate_clock;
VMSTATE_CLOCK_V(field, state, 0)
#define VMSTATE_CLOCK_V(field, state, version) \
VMSTATE_STRUCT_POINTER_V(field, state, version, vmstate_clock, Clock)
#define VMSTATE_ARRAY_CLOCK(field, state, num) \
VMSTATE_ARRAY_CLOCK_V(field, state, num, 0)
#define VMSTATE_ARRAY_CLOCK_V(field, state, num, version) \
VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(field, state, num, version, \
vmstate_clock, Clock)
/**
* clock_setup_canonical_path:

55
include/hw/gpio/npcm7xx_gpio.h Normal file
View file

@ -0,0 +1,55 @@
/*
* Nuvoton NPCM7xx General Purpose Input / Output (GPIO)
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef NPCM7XX_GPIO_H
#define NPCM7XX_GPIO_H
#include "exec/memory.h"
#include "hw/sysbus.h"
/* Number of pins managed by each controller. */
#define NPCM7XX_GPIO_NR_PINS (32)
/*
* Number of registers in our device state structure. Don't change this without
* incrementing the version_id in the vmstate.
*/
#define NPCM7XX_GPIO_NR_REGS (0x80 / sizeof(uint32_t))
typedef struct NPCM7xxGPIOState {
SysBusDevice parent;
/* Properties to be defined by the SoC */
uint32_t reset_pu;
uint32_t reset_pd;
uint32_t reset_osrc;
uint32_t reset_odsc;
MemoryRegion mmio;
qemu_irq irq;
qemu_irq output[NPCM7XX_GPIO_NR_PINS];
uint32_t pin_level;
uint32_t ext_level;
uint32_t ext_driven;
uint32_t regs[NPCM7XX_GPIO_NR_REGS];
} NPCM7xxGPIOState;
#define TYPE_NPCM7XX_GPIO "npcm7xx-gpio"
#define NPCM7XX_GPIO(obj) \
OBJECT_CHECK(NPCM7xxGPIOState, (obj), TYPE_NPCM7XX_GPIO)
#endif /* NPCM7XX_GPIO_H */

210
include/hw/misc/bcm2835_cprman.h Normal file
View file

@ -0,0 +1,210 @@
/*
* BCM2835 CPRMAN clock manager
*
* Copyright (c) 2020 Luc Michel <luc@lmichel.fr>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_MISC_CPRMAN_H
#define HW_MISC_CPRMAN_H
#include "hw/sysbus.h"
#include "hw/qdev-clock.h"
#define TYPE_BCM2835_CPRMAN "bcm2835-cprman"
typedef struct BCM2835CprmanState BCM2835CprmanState;
DECLARE_INSTANCE_CHECKER(BCM2835CprmanState, CPRMAN,
TYPE_BCM2835_CPRMAN)
#define CPRMAN_NUM_REGS (0x2000 / sizeof(uint32_t))
typedef enum CprmanPll {
CPRMAN_PLLA = 0,
CPRMAN_PLLC,
CPRMAN_PLLD,
CPRMAN_PLLH,
CPRMAN_PLLB,
CPRMAN_NUM_PLL
} CprmanPll;
typedef enum CprmanPllChannel {
CPRMAN_PLLA_CHANNEL_DSI0 = 0,
CPRMAN_PLLA_CHANNEL_CORE,
CPRMAN_PLLA_CHANNEL_PER,
CPRMAN_PLLA_CHANNEL_CCP2,
CPRMAN_PLLC_CHANNEL_CORE2,
CPRMAN_PLLC_CHANNEL_CORE1,
CPRMAN_PLLC_CHANNEL_PER,
CPRMAN_PLLC_CHANNEL_CORE0,
CPRMAN_PLLD_CHANNEL_DSI0,
CPRMAN_PLLD_CHANNEL_CORE,
CPRMAN_PLLD_CHANNEL_PER,
CPRMAN_PLLD_CHANNEL_DSI1,
CPRMAN_PLLH_CHANNEL_AUX,
CPRMAN_PLLH_CHANNEL_RCAL,
CPRMAN_PLLH_CHANNEL_PIX,
CPRMAN_PLLB_CHANNEL_ARM,
CPRMAN_NUM_PLL_CHANNEL,
/* Special values used when connecting clock sources to clocks */
CPRMAN_CLOCK_SRC_NORMAL = -1,
CPRMAN_CLOCK_SRC_FORCE_GROUND = -2,
CPRMAN_CLOCK_SRC_DSI0HSCK = -3,
} CprmanPllChannel;
typedef enum CprmanClockMux {
CPRMAN_CLOCK_GNRIC,
CPRMAN_CLOCK_VPU,
CPRMAN_CLOCK_SYS,
CPRMAN_CLOCK_PERIA,
CPRMAN_CLOCK_PERII,
CPRMAN_CLOCK_H264,
CPRMAN_CLOCK_ISP,
CPRMAN_CLOCK_V3D,
CPRMAN_CLOCK_CAM0,
CPRMAN_CLOCK_CAM1,
CPRMAN_CLOCK_CCP2,
CPRMAN_CLOCK_DSI0E,
CPRMAN_CLOCK_DSI0P,
CPRMAN_CLOCK_DPI,
CPRMAN_CLOCK_GP0,
CPRMAN_CLOCK_GP1,
CPRMAN_CLOCK_GP2,
CPRMAN_CLOCK_HSM,
CPRMAN_CLOCK_OTP,
CPRMAN_CLOCK_PCM,
CPRMAN_CLOCK_PWM,
CPRMAN_CLOCK_SLIM,
CPRMAN_CLOCK_SMI,
CPRMAN_CLOCK_TEC,
CPRMAN_CLOCK_TD0,
CPRMAN_CLOCK_TD1,
CPRMAN_CLOCK_TSENS,
CPRMAN_CLOCK_TIMER,
CPRMAN_CLOCK_UART,
CPRMAN_CLOCK_VEC,
CPRMAN_CLOCK_PULSE,
CPRMAN_CLOCK_SDC,
CPRMAN_CLOCK_ARM,
CPRMAN_CLOCK_AVEO,
CPRMAN_CLOCK_EMMC,
CPRMAN_CLOCK_EMMC2,
CPRMAN_NUM_CLOCK_MUX
} CprmanClockMux;
typedef enum CprmanClockMuxSource {
CPRMAN_CLOCK_SRC_GND = 0,
CPRMAN_CLOCK_SRC_XOSC,
CPRMAN_CLOCK_SRC_TD0,
CPRMAN_CLOCK_SRC_TD1,
CPRMAN_CLOCK_SRC_PLLA,
CPRMAN_CLOCK_SRC_PLLC,
CPRMAN_CLOCK_SRC_PLLD,
CPRMAN_CLOCK_SRC_PLLH,
CPRMAN_CLOCK_SRC_PLLC_CORE1,
CPRMAN_CLOCK_SRC_PLLC_CORE2,
CPRMAN_NUM_CLOCK_MUX_SRC
} CprmanClockMuxSource;
typedef struct CprmanPllState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
CprmanPll id;
uint32_t *reg_cm;
uint32_t *reg_a2w_ctrl;
uint32_t *reg_a2w_ana; /* ANA[0] .. ANA[3] */
uint32_t prediv_mask; /* prediv bit in ana[1] */
uint32_t *reg_a2w_frac;
Clock *xosc_in;
Clock *out;
} CprmanPllState;
typedef struct CprmanPllChannelState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
CprmanPllChannel id;
CprmanPll parent;
uint32_t *reg_cm;
uint32_t hold_mask;
uint32_t load_mask;
uint32_t *reg_a2w_ctrl;
int fixed_divider;
Clock *pll_in;
Clock *out;
} CprmanPllChannelState;
typedef struct CprmanClockMuxState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
CprmanClockMux id;
uint32_t *reg_ctl;
uint32_t *reg_div;
int int_bits;
int frac_bits;
Clock *srcs[CPRMAN_NUM_CLOCK_MUX_SRC];
Clock *out;
/*
* Used by clock srcs update callback to retrieve both the clock and the
* source number.
*/
struct CprmanClockMuxState *backref[CPRMAN_NUM_CLOCK_MUX_SRC];
} CprmanClockMuxState;
typedef struct CprmanDsi0HsckMuxState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
CprmanClockMux id;
uint32_t *reg_cm;
Clock *plla_in;
Clock *plld_in;
Clock *out;
} CprmanDsi0HsckMuxState;
struct BCM2835CprmanState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
CprmanPllState plls[CPRMAN_NUM_PLL];
CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL];
CprmanClockMuxState clock_muxes[CPRMAN_NUM_CLOCK_MUX];
CprmanDsi0HsckMuxState dsi0hsck_mux;
uint32_t regs[CPRMAN_NUM_REGS];
uint32_t xosc_freq;
Clock *xosc;
Clock *gnd;
};
#endif

1019
include/hw/misc/bcm2835_cprman_internals.h Normal file
View file

File diff suppressed because it is too large Load diff

2
include/hw/misc/npcm7xx_clk.h
View file

@ -31,6 +31,8 @@
*/
#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
typedef struct NPCM7xxCLKState {
SysBusDevice parent;

34
include/hw/misc/npcm7xx_rng.h Normal file
View file

@ -0,0 +1,34 @@
/*
* Nuvoton NPCM7xx Random Number Generator.
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#ifndef NPCM7XX_RNG_H
#define NPCM7XX_RNG_H
#include "hw/sysbus.h"
typedef struct NPCM7xxRNGState {
SysBusDevice parent;
MemoryRegion iomem;
uint8_t rngcs;
uint8_t rngd;
uint8_t rngmode;
} NPCM7xxRNGState;
#define TYPE_NPCM7XX_RNG "npcm7xx-rng"
#define NPCM7XX_RNG(obj) OBJECT_CHECK(NPCM7xxRNGState, (obj), TYPE_NPCM7XX_RNG)
#endif /* NPCM7XX_RNG_H */

3
include/hw/timer/armv7m_systick.h
View file

@ -14,6 +14,7 @@
#include "hw/sysbus.h"
#include "qom/object.h"
#include "hw/ptimer.h"
#define TYPE_SYSTICK "armv7m_systick"
@ -27,7 +28,7 @@ struct SysTickState {
uint32_t control;
uint32_t reload;
int64_t tick;
QEMUTimer *timer;
ptimer_state *ptimer;
MemoryRegion iomem;
qemu_irq irq;
};

48
include/hw/timer/npcm7xx_timer.h
View file

@ -29,14 +29,31 @@
*/
#define NPCM7XX_TIMER_NR_REGS (0x54 / sizeof(uint32_t))
/* The basic watchdog timer period is 2^14 clock cycles. */
#define NPCM7XX_WATCHDOG_BASETIME_SHIFT 14
#define NPCM7XX_WATCHDOG_RESET_GPIO_OUT "npcm7xx-clk-watchdog-reset-gpio-out"
typedef struct NPCM7xxTimerCtrlState NPCM7xxTimerCtrlState;
/**
* struct NPCM7xxTimer - Individual timer state.
* @irq: GIC interrupt line to fire on expiration (if enabled).
* struct NPCM7xxBaseTimer - Basic functionality that both regular timer and
* watchdog timer use.
* @qtimer: QEMU timer that notifies us on expiration.
* @expires_ns: Absolute virtual expiration time.
* @remaining_ns: Remaining time until expiration if timer is paused.
*/
typedef struct NPCM7xxBaseTimer {
QEMUTimer qtimer;
int64_t expires_ns;
int64_t remaining_ns;
} NPCM7xxBaseTimer;
/**
* struct NPCM7xxTimer - Individual timer state.
* @ctrl: The timer module that owns this timer.
* @irq: GIC interrupt line to fire on expiration (if enabled).
* @base_timer: The basic timer functionality for this timer.
* @tcsr: The Timer Control and Status Register.
* @ticr: The Timer Initial Count Register.
*/
@ -44,21 +61,38 @@ typedef struct NPCM7xxTimer {
NPCM7xxTimerCtrlState *ctrl;
qemu_irq irq;
QEMUTimer qtimer;
int64_t expires_ns;
int64_t remaining_ns;
NPCM7xxBaseTimer base_timer;
uint32_t tcsr;
uint32_t ticr;
} NPCM7xxTimer;
/**
* struct NPCM7xxWatchdogTimer - The watchdog timer state.
* @ctrl: The timer module that owns this timer.
* @irq: GIC interrupt line to fire on expiration (if enabled).
* @reset_signal: The GPIO used to send a reset signal.
* @base_timer: The basic timer functionality for this timer.
* @wtcr: The Watchdog Timer Control Register.
*/
typedef struct NPCM7xxWatchdogTimer {
NPCM7xxTimerCtrlState *ctrl;
qemu_irq irq;
qemu_irq reset_signal;
NPCM7xxBaseTimer base_timer;
uint32_t wtcr;
} NPCM7xxWatchdogTimer;
/**
* struct NPCM7xxTimerCtrlState - Timer Module device state.
* @parent: System bus device.
* @iomem: Memory region through which registers are accessed.
* @index: The index of this timer module.
* @tisr: The Timer Interrupt Status Register.
* @wtcr: The Watchdog Timer Control Register.
* @timer: The five individual timers managed by this module.
* @watchdog_timer: The watchdog timer managed by this module.
*/
struct NPCM7xxTimerCtrlState {
SysBusDevice parent;
@ -66,9 +100,9 @@ struct NPCM7xxTimerCtrlState {
MemoryRegion iomem;
uint32_t tisr;
uint32_t wtcr;
NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
NPCM7xxWatchdogTimer watchdog_timer;
};
#define TYPE_NPCM7XX_TIMER "npcm7xx-timer"

79
include/hw/watchdog/sbsa_gwdt.h Normal file
View file

@ -0,0 +1,79 @@
/*
* Copyright (c) 2020 Linaro Limited
*
* Authors:
* Shashi Mallela <shashi.mallela@linaro.org>
*
* This work is licensed under the terms of the GNU GPL, version 2 or (at your
* option) any later version. See the COPYING file in the top-level directory.
*
*/
#ifndef WDT_SBSA_GWDT_H
#define WDT_SBSA_GWDT_H
#include "qemu/bitops.h"
#include "hw/sysbus.h"
#include "hw/irq.h"
#define TYPE_WDT_SBSA "sbsa_gwdt"
#define SBSA_GWDT(obj) \
OBJECT_CHECK(SBSA_GWDTState, (obj), TYPE_WDT_SBSA)
#define SBSA_GWDT_CLASS(klass) \
OBJECT_CLASS_CHECK(SBSA_GWDTClass, (klass), TYPE_WDT_SBSA)
#define SBSA_GWDT_GET_CLASS(obj) \
OBJECT_GET_CLASS(SBSA_GWDTClass, (obj), TYPE_WDT_SBSA)
/* SBSA Generic Watchdog register definitions */
/* refresh frame */
#define SBSA_GWDT_WRR 0x000
/* control frame */
#define SBSA_GWDT_WCS 0x000
#define SBSA_GWDT_WOR 0x008
#define SBSA_GWDT_WORU 0x00C
#define SBSA_GWDT_WCV 0x010
#define SBSA_GWDT_WCVU 0x014
/* Watchdog Interface Identification Register */
#define SBSA_GWDT_W_IIDR 0xFCC
/* Watchdog Control and Status Register Bits */
#define SBSA_GWDT_WCS_EN BIT(0)
#define SBSA_GWDT_WCS_WS0 BIT(1)
#define SBSA_GWDT_WCS_WS1 BIT(2)
#define SBSA_GWDT_WOR_MASK 0x0000FFFF
/*
* Watchdog Interface Identification Register definition
* considering JEP106 code for ARM in Bits [11:0]
*/
#define SBSA_GWDT_ID 0x1043B
/* 2 Separate memory regions for each of refresh & control register frames */
#define SBSA_GWDT_RMMIO_SIZE 0x1000
#define SBSA_GWDT_CMMIO_SIZE 0x1000
#define SBSA_TIMER_FREQ 62500000 /* Hz */
typedef struct SBSA_GWDTState {
/* <private> */
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion rmmio;
MemoryRegion cmmio;
qemu_irq irq;
QEMUTimer *timer;
uint32_t id;
uint32_t wcs;
uint32_t worl;
uint32_t woru;
uint32_t wcvl;
uint32_t wcvu;
} SBSA_GWDTState;
#endif /* WDT_SBSA_GWDT_H */