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target/riscv: support for 128-bit arithmetic instructions

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Addition of 128-bit adds and subs in their various sizes,
"set if less than"s and branches.
Refactored the code to have a comparison function used for both stls and
branches.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-14-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frédéric Pétrot 2022-01-06 22:01:03 +01:00 • committed by Alistair Francis
parent 6bf4bbed20
commit 7fd40f8679
5 changed files with 222 additions and 49 deletions
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20
target/riscv/insn_trans/trans_rvb.c.inc
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@ -104,25 +104,25 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
static bool trans_min(DisasContext *ctx, arg_min *a)
{
REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl, NULL);
}
static bool trans_max(DisasContext *ctx, arg_max *a)
{
REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl, NULL);
}
static bool trans_minu(DisasContext *ctx, arg_minu *a)
{
REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl, NULL);
}
static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
{
REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl, NULL);
}
static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
@ -357,7 +357,7 @@ GEN_SHADD(3)
static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
{ \
REQUIRE_ZBA(ctx); \
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add); \
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add, NULL); \
}
GEN_TRANS_SHADD(1)
@ -447,7 +447,7 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
{ \
REQUIRE_64BIT(ctx); \
REQUIRE_ZBA(ctx); \
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw); \
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw, NULL); \
}
GEN_TRANS_SHADD_UW(1)
@ -466,7 +466,7 @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBA(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
return gen_arith(ctx, a, EXT_NONE, gen_add_uw, NULL);
}
static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
@ -484,7 +484,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
{
REQUIRE_ZBC(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
}
static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
@ -496,11 +496,11 @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
{
REQUIRE_ZBC(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
}
static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
{
REQUIRE_ZBC(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
}