mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-07-27 04:13:53 -06:00
hw/arm: Add NPCM845 Evaluation board
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-17-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Hao Wu
Peter Maydell
parent
ae0c4d1a12
commit
7e70eb3cad
3 changed files with 275 additions and 1 deletions
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@ -12,7 +12,7 @@ arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
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arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
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arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
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arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
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arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
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arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
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arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
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arm_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm8xx.c'))
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arm_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm8xx.c', 'npcm8xx_boards.c'))
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arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
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arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
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arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
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arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
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arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
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arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
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253
hw/arm/npcm8xx_boards.c
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253
hw/arm/npcm8xx_boards.c
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@ -0,0 +1,253 @@
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/*
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* Machine definitions for boards featuring an NPCM8xx SoC.
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*
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* Copyright 2021 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "chardev/char.h"
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#include "hw/arm/npcm8xx.h"
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#include "hw/core/cpu.h"
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#include "hw/loader.h"
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#include "hw/qdev-core.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/datadir.h"
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#include "qemu/units.h"
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#define NPCM845_EVB_POWER_ON_STRAPS 0x000017ff
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static const char npcm8xx_default_bootrom[] = "npcm8xx_bootrom.bin";
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static void npcm8xx_load_bootrom(MachineState *machine, NPCM8xxState *soc)
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{
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const char *bios_name = machine->firmware ?: npcm8xx_default_bootrom;
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g_autofree char *filename = NULL;
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int ret;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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if (!filename) {
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error_report("Could not find ROM image '%s'", bios_name);
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if (!machine->kernel_filename) {
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/* We can't boot without a bootrom or a kernel image. */
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exit(1);
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}
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return;
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}
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ret = load_image_mr(filename, machine->ram);
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if (ret < 0) {
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error_report("Failed to load ROM image '%s'", filename);
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exit(1);
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}
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}
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static void npcm8xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no,
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const char *flash_type, DriveInfo *dinfo)
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{
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DeviceState *flash;
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qemu_irq flash_cs;
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flash = qdev_new(flash_type);
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if (dinfo) {
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qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo));
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}
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qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal);
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flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0);
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qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs);
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}
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static void npcm8xx_connect_dram(NPCM8xxState *soc, MemoryRegion *dram)
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{
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memory_region_add_subregion(get_system_memory(), NPCM8XX_DRAM_BA, dram);
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object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram),
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&error_abort);
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}
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static NPCM8xxState *npcm8xx_create_soc(MachineState *machine,
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uint32_t hw_straps)
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{
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NPCM8xxMachineClass *nmc = NPCM8XX_MACHINE_GET_CLASS(machine);
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Object *obj;
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obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc",
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&error_abort, NULL);
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object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort);
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return NPCM8XX(obj);
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}
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static I2CBus *npcm8xx_i2c_get_bus(NPCM8xxState *soc, uint32_t num)
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{
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g_assert(num < ARRAY_SIZE(soc->smbus));
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return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus"));
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}
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static void npcm8xx_init_pwm_splitter(NPCM8xxMachine *machine,
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NPCM8xxState *soc, const int *fan_counts)
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{
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SplitIRQ *splitters = machine->fan_splitter;
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/*
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* PWM 0~3 belong to module 0 output 0~3.
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* PWM 4~7 belong to module 1 output 0~3.
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*/
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for (int i = 0; i < NPCM8XX_NR_PWM_MODULES; ++i) {
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for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) {
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int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j;
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DeviceState *splitter;
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if (fan_counts[splitter_no] < 1) {
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continue;
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}
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object_initialize_child(OBJECT(machine), "fan-splitter[*]",
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&splitters[splitter_no], TYPE_SPLIT_IRQ);
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splitter = DEVICE(&splitters[splitter_no]);
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qdev_prop_set_uint16(splitter, "num-lines",
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fan_counts[splitter_no]);
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qdev_realize(splitter, NULL, &error_abort);
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qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out",
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j, qdev_get_gpio_in(splitter, 0));
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}
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}
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}
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static void npcm8xx_connect_pwm_fan(NPCM8xxState *soc, SplitIRQ *splitter,
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int fan_no, int output_no)
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{
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DeviceState *fan;
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int fan_input;
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qemu_irq fan_duty_gpio;
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g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT);
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/*
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* Fan 0~1 belong to module 0 input 0~1.
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* Fan 2~3 belong to module 1 input 0~1.
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* ...
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* Fan 14~15 belong to module 7 input 0~1.
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* Fan 16~17 belong to module 0 input 2~3.
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* Fan 18~19 belong to module 1 input 2~3.
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*/
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if (fan_no < 16) {
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fan = DEVICE(&soc->mft[fan_no / 2]);
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fan_input = fan_no % 2;
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} else {
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fan = DEVICE(&soc->mft[(fan_no - 16) / 2]);
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fan_input = fan_no % 2 + 2;
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}
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/* Connect the Fan to PWM module */
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fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input);
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qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio);
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}
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static void npcm845_evb_i2c_init(NPCM8xxState *soc)
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{
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/* tmp100 temperature sensor on SVB, tmp105 is compatible */
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i2c_slave_create_simple(npcm8xx_i2c_get_bus(soc, 6), "tmp105", 0x48);
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}
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static void npcm845_evb_fan_init(NPCM8xxMachine *machine, NPCM8xxState *soc)
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{
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SplitIRQ *splitter = machine->fan_splitter;
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static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0};
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npcm8xx_init_pwm_splitter(machine, soc, fan_counts);
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npcm8xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
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npcm8xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
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npcm8xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
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npcm8xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
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npcm8xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
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npcm8xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
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npcm8xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0);
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npcm8xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1);
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npcm8xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0);
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npcm8xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1);
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npcm8xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0);
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npcm8xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1);
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npcm8xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0);
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npcm8xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1);
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npcm8xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0);
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npcm8xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1);
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}
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static void npcm845_evb_init(MachineState *machine)
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{
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NPCM8xxState *soc;
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soc = npcm8xx_create_soc(machine, NPCM845_EVB_POWER_ON_STRAPS);
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npcm8xx_connect_dram(soc, machine->ram);
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qdev_realize(DEVICE(soc), NULL, &error_fatal);
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npcm8xx_load_bootrom(machine, soc);
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npcm8xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
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npcm845_evb_i2c_init(soc);
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npcm845_evb_fan_init(NPCM8XX_MACHINE(machine), soc);
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npcm8xx_load_kernel(machine, soc);
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}
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static void npcm8xx_set_soc_type(NPCM8xxMachineClass *nmc, const char *type)
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{
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NPCM8xxClass *sc = NPCM8XX_CLASS(object_class_by_name(type));
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MachineClass *mc = MACHINE_CLASS(nmc);
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nmc->soc_type = type;
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mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus;
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}
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static void npcm8xx_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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static const char * const valid_cpu_types[] = {
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ARM_CPU_TYPE_NAME("cortex-a9"),
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NULL
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};
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mc->no_floppy = 1;
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mc->no_cdrom = 1;
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mc->no_parallel = 1;
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mc->default_ram_id = "ram";
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mc->valid_cpu_types = valid_cpu_types;
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}
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static void npcm845_evb_machine_class_init(ObjectClass *oc, void *data)
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{
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NPCM8xxMachineClass *nmc = NPCM8XX_MACHINE_CLASS(oc);
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MachineClass *mc = MACHINE_CLASS(oc);
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npcm8xx_set_soc_type(nmc, TYPE_NPCM8XX);
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mc->desc = "Nuvoton NPCM845 Evaluation Board (Cortex-A35)";
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mc->init = npcm845_evb_init;
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mc->default_ram_size = 1 * GiB;
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};
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static const TypeInfo npcm8xx_machine_types[] = {
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{
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.name = TYPE_NPCM8XX_MACHINE,
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.parent = TYPE_MACHINE,
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.instance_size = sizeof(NPCM8xxMachine),
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.class_size = sizeof(NPCM8xxMachineClass),
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.class_init = npcm8xx_machine_class_init,
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.abstract = true,
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}, {
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.name = MACHINE_TYPE_NAME("npcm845-evb"),
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.parent = TYPE_NPCM8XX_MACHINE,
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.class_init = npcm845_evb_machine_class_init,
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},
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};
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DEFINE_TYPES(npcm8xx_machine_types)
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@ -51,6 +51,27 @@
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#define NPCM8XX_NR_PWM_MODULES 3
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#define NPCM8XX_NR_PWM_MODULES 3
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struct NPCM8xxMachine {
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MachineState parent_obj;
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/*
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* PWM fan splitter. each splitter connects to one PWM output and
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* multiple MFT inputs.
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*/
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SplitIRQ fan_splitter[NPCM8XX_NR_PWM_MODULES *
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NPCM7XX_PWM_PER_MODULE];
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};
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struct NPCM8xxMachineClass {
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MachineClass parent_class;
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const char *soc_type;
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};
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#define TYPE_NPCM8XX_MACHINE MACHINE_TYPE_NAME("npcm8xx")
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OBJECT_DECLARE_TYPE(NPCM8xxMachine, NPCM8xxMachineClass, NPCM8XX_MACHINE)
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struct NPCM8xxState {
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struct NPCM8xxState {
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DeviceState parent_obj;
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DeviceState parent_obj;
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