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target/i386: Enable fdp-excptn-only and zero-fcs-fds

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- CPUID.(EAX=07H,ECX=0H):EBX[bit 6]: x87 FPU Data Pointer updated only
  on x87 exceptions if 1.

- CPUID.(EAX=07H,ECX=0H):EBX[bit 13]: Deprecates FPU CS and FPU DS
  values if 1. i.e., X87 FCS and FDS are always zero.

Define names for them so that they can be exposed to guest with -cpu host.

Also define the bit field MACROs so that named cpu models can add it as
well in the future.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Link: https://lore.kernel.org/r/20240814075431.339209-3-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Xiaoyao Li 2024-08-14 03:54:24 -04:00 • committed by Paolo Bonzini
parent 00c8a933d9
commit 7dddc3bb87
2 changed files with 6 additions and 2 deletions
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4
target/i386/cpu.c
View file

@ -1054,9 +1054,9 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.type = CPUID_FEATURE_WORD, .type = CPUID_FEATURE_WORD,
.feat_names = { .feat_names = {
"fsgsbase", "tsc-adjust", "sgx", "bmi1", "fsgsbase", "tsc-adjust", "sgx", "bmi1",
"hle", "avx2", NULL, "smep", "hle", "avx2", "fdp-excptn-only", "smep",
"bmi2", "erms", "invpcid", "rtm", "bmi2", "erms", "invpcid", "rtm",
NULL, NULL, "mpx", NULL, NULL, "zero-fcs-fds", "mpx", NULL,
"avx512f", "avx512dq", "rdseed", "adx", "avx512f", "avx512dq", "rdseed", "adx",
"smap", "avx512ifma", "pcommit", "clflushopt", "smap", "avx512ifma", "pcommit", "clflushopt",
"clwb", "intel-pt", "avx512pf", "avx512er", "clwb", "intel-pt", "avx512pf", "avx512er",

4
target/i386/cpu.h
View file

@ -820,6 +820,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
#define CPUID_7_0_EBX_HLE (1U << 4) #define CPUID_7_0_EBX_HLE (1U << 4)
/* Intel Advanced Vector Extensions 2 */ /* Intel Advanced Vector Extensions 2 */
#define CPUID_7_0_EBX_AVX2 (1U << 5) #define CPUID_7_0_EBX_AVX2 (1U << 5)
/* FPU data pointer updated only on x87 exceptions */
#define CPUID_7_0_EBX_FDP_EXCPTN_ONLY (1u << 6)
/* Supervisor-mode Execution Prevention */ /* Supervisor-mode Execution Prevention */
#define CPUID_7_0_EBX_SMEP (1U << 7) #define CPUID_7_0_EBX_SMEP (1U << 7)
/* 2nd Group of Advanced Bit Manipulation Extensions */ /* 2nd Group of Advanced Bit Manipulation Extensions */
@ -830,6 +832,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
#define CPUID_7_0_EBX_INVPCID (1U << 10) #define CPUID_7_0_EBX_INVPCID (1U << 10)
/* Restricted Transactional Memory */ /* Restricted Transactional Memory */
#define CPUID_7_0_EBX_RTM (1U << 11) #define CPUID_7_0_EBX_RTM (1U << 11)
/* Zero out FPU CS and FPU DS */
#define CPUID_7_0_EBX_ZERO_FCS_FDS (1U << 13)
/* Memory Protection Extension */ /* Memory Protection Extension */
#define CPUID_7_0_EBX_MPX (1U << 14) #define CPUID_7_0_EBX_MPX (1U << 14)
/* AVX-512 Foundation */ /* AVX-512 Foundation */