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Handle all MMU models in switches, even if it's just to abort because of lack

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of supporting code.
Implement 74xx software TLB model.
Keep 74xx with software TLB disabled, as Linux is not able to handle TLB miss
  on those processors.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3307 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-10-01 05:16:57 +00:00
parent 578bb25230
commit 7dbe11acd8
5 changed files with 169 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

21
target-ppc/op_helper.c
View file

@ -2363,6 +2363,27 @@ void do_load_6xx_tlb (int is_code)
way, is_code, CMP, RPN);
}
void do_load_74xx_tlb (int is_code)
{
target_ulong RPN, CMP, EPN;
int way;
RPN = env->spr[SPR_PTELO];
CMP = env->spr[SPR_PTEHI];
EPN = env->spr[SPR_TLBMISS] & ~0x3;
way = env->spr[SPR_TLBMISS] & 0x3;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
__func__, (unsigned long)T0, (unsigned long)EPN,
(unsigned long)CMP, (unsigned long)RPN, way);
}
#endif
/* Store this TLB */
ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
}
static target_ulong booke_tlb_to_page_size (int size)
{
return 1024 << (2 * size);