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target-mips: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc] sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber
parent
68cee38a9c
commit
7db13fae2c
5 changed files with 274 additions and 274 deletions
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@ -29,10 +29,10 @@
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#endif /* !defined(CONFIG_USER_ONLY) */
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#ifndef CONFIG_USER_ONLY
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static inline void cpu_mips_tlb_flush (CPUState *env, int flush_global);
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static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
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#endif
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static inline void compute_hflags(CPUState *env)
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static inline void compute_hflags(CPUMIPSState *env)
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{
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env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
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MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
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@ -750,14 +750,14 @@ void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
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#ifndef CONFIG_USER_ONLY
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/* SMP helpers. */
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static int mips_vpe_is_wfi(CPUState *c)
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static int mips_vpe_is_wfi(CPUMIPSState *c)
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{
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/* If the VPE is halted but otherwise active, it means it's waiting for
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an interrupt. */
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return c->halted && mips_vpe_active(c);
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}
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static inline void mips_vpe_wake(CPUState *c)
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static inline void mips_vpe_wake(CPUMIPSState *c)
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{
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/* Dont set ->halted = 0 directly, let it be done via cpu_has_work
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because there might be other conditions that state that c should
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@ -765,7 +765,7 @@ static inline void mips_vpe_wake(CPUState *c)
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cpu_interrupt(c, CPU_INTERRUPT_WAKE);
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}
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static inline void mips_vpe_sleep(CPUState *c)
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static inline void mips_vpe_sleep(CPUMIPSState *c)
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{
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/* The VPE was shut off, really go to bed.
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Reset any old _WAKE requests. */
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@ -773,7 +773,7 @@ static inline void mips_vpe_sleep(CPUState *c)
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cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE);
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}
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static inline void mips_tc_wake(CPUState *c, int tc)
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static inline void mips_tc_wake(CPUMIPSState *c, int tc)
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{
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/* FIXME: TC reschedule. */
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if (mips_vpe_active(c) && !mips_vpe_is_wfi(c)) {
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@ -781,7 +781,7 @@ static inline void mips_tc_wake(CPUState *c, int tc)
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}
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}
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static inline void mips_tc_sleep(CPUState *c, int tc)
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static inline void mips_tc_sleep(CPUMIPSState *c, int tc)
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{
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/* FIXME: TC reschedule. */
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if (!mips_vpe_active(c)) {
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@ -791,14 +791,14 @@ static inline void mips_tc_sleep(CPUState *c, int tc)
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/* tc should point to an int with the value of the global TC index.
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This function will transform it into a local index within the
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returned CPUState.
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returned CPUMIPSState.
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FIXME: This code assumes that all VPEs have the same number of TCs,
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which depends on runtime setup. Can probably be fixed by
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walking the list of CPUStates. */
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static CPUState *mips_cpu_map_tc(int *tc)
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walking the list of CPUMIPSStates. */
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static CPUMIPSState *mips_cpu_map_tc(int *tc)
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{
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CPUState *other;
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CPUMIPSState *other;
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int vpe_idx, nr_threads = env->nr_threads;
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int tc_idx = *tc;
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@ -823,7 +823,7 @@ static CPUState *mips_cpu_map_tc(int *tc)
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These helper call synchronizes the regs for a given cpu. */
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/* Called for updates to CP0_Status. */
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static void sync_c0_status(CPUState *cpu, int tc)
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static void sync_c0_status(CPUMIPSState *cpu, int tc)
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{
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int32_t tcstatus, *tcst;
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uint32_t v = cpu->CP0_Status;
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@ -858,7 +858,7 @@ static void sync_c0_status(CPUState *cpu, int tc)
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}
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/* Called for updates to CP0_TCStatus. */
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static void sync_c0_tcstatus(CPUState *cpu, int tc, target_ulong v)
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static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, target_ulong v)
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{
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uint32_t status;
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uint32_t tcu, tmx, tasid, tksu;
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@ -889,7 +889,7 @@ static void sync_c0_tcstatus(CPUState *cpu, int tc, target_ulong v)
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}
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/* Called for updates to CP0_EntryHi. */
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static void sync_c0_entryhi(CPUState *cpu, int tc)
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static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
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{
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int32_t *tcst;
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uint32_t asid, v = cpu->CP0_EntryHi;
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@ -935,7 +935,7 @@ target_ulong helper_mfc0_tcstatus (void)
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target_ulong helper_mftc0_tcstatus(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc)
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return other->active_tc.CP0_TCStatus;
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@ -951,7 +951,7 @@ target_ulong helper_mfc0_tcbind (void)
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target_ulong helper_mftc0_tcbind(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc)
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return other->active_tc.CP0_TCBind;
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@ -967,7 +967,7 @@ target_ulong helper_mfc0_tcrestart (void)
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target_ulong helper_mftc0_tcrestart(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc)
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return other->active_tc.PC;
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@ -983,7 +983,7 @@ target_ulong helper_mfc0_tchalt (void)
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target_ulong helper_mftc0_tchalt(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc)
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return other->active_tc.CP0_TCHalt;
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@ -999,7 +999,7 @@ target_ulong helper_mfc0_tccontext (void)
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target_ulong helper_mftc0_tccontext(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc)
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return other->active_tc.CP0_TCContext;
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@ -1015,7 +1015,7 @@ target_ulong helper_mfc0_tcschedule (void)
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target_ulong helper_mftc0_tcschedule(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc)
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return other->active_tc.CP0_TCSchedule;
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@ -1031,7 +1031,7 @@ target_ulong helper_mfc0_tcschefback (void)
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target_ulong helper_mftc0_tcschefback(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc)
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return other->active_tc.CP0_TCScheFBack;
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@ -1047,7 +1047,7 @@ target_ulong helper_mfc0_count (void)
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target_ulong helper_mftc0_entryhi(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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return other->CP0_EntryHi;
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}
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@ -1056,7 +1056,7 @@ target_ulong helper_mftc0_cause(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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int32_t tccause;
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc) {
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tccause = other->CP0_Cause;
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@ -1070,7 +1070,7 @@ target_ulong helper_mftc0_cause(void)
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target_ulong helper_mftc0_status(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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return other->CP0_Status;
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}
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@ -1103,7 +1103,7 @@ target_ulong helper_mftc0_debug(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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int32_t tcstatus;
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc)
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tcstatus = other->active_tc.CP0_Debug_tcstatus;
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@ -1201,7 +1201,7 @@ void helper_mtc0_vpecontrol (target_ulong arg1)
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void helper_mttc0_vpecontrol(target_ulong arg1)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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uint32_t mask;
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uint32_t newval;
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@ -1217,7 +1217,7 @@ void helper_mttc0_vpecontrol(target_ulong arg1)
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target_ulong helper_mftc0_vpecontrol(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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/* FIXME: Mask away return zero on read bits. */
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return other->CP0_VPEControl;
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}
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@ -1225,7 +1225,7 @@ target_ulong helper_mftc0_vpecontrol(void)
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target_ulong helper_mftc0_vpeconf0(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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return other->CP0_VPEConf0;
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}
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@ -1250,7 +1250,7 @@ void helper_mtc0_vpeconf0 (target_ulong arg1)
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void helper_mttc0_vpeconf0(target_ulong arg1)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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uint32_t mask = 0;
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uint32_t newval;
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@ -1311,7 +1311,7 @@ void helper_mtc0_tcstatus (target_ulong arg1)
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void helper_mttc0_tcstatus (target_ulong arg1)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc)
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other->active_tc.CP0_TCStatus = arg1;
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@ -1336,7 +1336,7 @@ void helper_mttc0_tcbind (target_ulong arg1)
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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uint32_t mask = (1 << CP0TCBd_TBE);
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uint32_t newval;
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
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mask |= (1 << CP0TCBd_CurVPE);
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@ -1360,7 +1360,7 @@ void helper_mtc0_tcrestart (target_ulong arg1)
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void helper_mttc0_tcrestart (target_ulong arg1)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc) {
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other->active_tc.PC = arg1;
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@ -1390,7 +1390,7 @@ void helper_mtc0_tchalt (target_ulong arg1)
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void helper_mttc0_tchalt (target_ulong arg1)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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// TODO: Halt TC / Restart (if allocated+active) TC.
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@ -1414,7 +1414,7 @@ void helper_mtc0_tccontext (target_ulong arg1)
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void helper_mttc0_tccontext (target_ulong arg1)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc)
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other->active_tc.CP0_TCContext = arg1;
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@ -1430,7 +1430,7 @@ void helper_mtc0_tcschedule (target_ulong arg1)
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void helper_mttc0_tcschedule (target_ulong arg1)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc)
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other->active_tc.CP0_TCSchedule = arg1;
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@ -1446,7 +1446,7 @@ void helper_mtc0_tcschefback (target_ulong arg1)
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void helper_mttc0_tcschefback (target_ulong arg1)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc)
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other->active_tc.CP0_TCScheFBack = arg1;
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@ -1542,7 +1542,7 @@ void helper_mtc0_entryhi (target_ulong arg1)
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void helper_mttc0_entryhi(target_ulong arg1)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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other->CP0_EntryHi = arg1;
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sync_c0_entryhi(other, other_tc);
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@ -1584,7 +1584,7 @@ void helper_mtc0_status (target_ulong arg1)
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void helper_mttc0_status(target_ulong arg1)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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other->CP0_Status = arg1 & ~0xf1000018;
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sync_c0_status(other, other_tc);
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@ -1602,7 +1602,7 @@ void helper_mtc0_srsctl (target_ulong arg1)
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env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
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}
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static void mtc0_cause(CPUState *cpu, target_ulong arg1)
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static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
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{
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uint32_t mask = 0x00C00300;
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uint32_t old = cpu->CP0_Cause;
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@ -1638,7 +1638,7 @@ void helper_mtc0_cause(target_ulong arg1)
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void helper_mttc0_cause(target_ulong arg1)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
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mtc0_cause(other, arg1);
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}
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@ -1646,7 +1646,7 @@ void helper_mttc0_cause(target_ulong arg1)
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target_ulong helper_mftc0_epc(void)
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||||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
|
||||
return other->CP0_EPC;
|
||||
}
|
||||
|
|
@ -1654,7 +1654,7 @@ target_ulong helper_mftc0_epc(void)
|
|||
target_ulong helper_mftc0_ebase(void)
|
||||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
|
||||
return other->CP0_EBase;
|
||||
}
|
||||
|
|
@ -1668,14 +1668,14 @@ void helper_mtc0_ebase (target_ulong arg1)
|
|||
void helper_mttc0_ebase(target_ulong arg1)
|
||||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
|
||||
}
|
||||
|
||||
target_ulong helper_mftc0_configx(target_ulong idx)
|
||||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
|
||||
switch (idx) {
|
||||
case 0: return other->CP0_Config0;
|
||||
|
|
@ -1746,7 +1746,7 @@ void helper_mttc0_debug(target_ulong arg1)
|
|||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
|
||||
/* XXX: Might be wrong, check with EJTAG spec. */
|
||||
if (other_tc == other->current_tc)
|
||||
|
|
@ -1787,7 +1787,7 @@ void helper_mtc0_datahi (target_ulong arg1)
|
|||
target_ulong helper_mftgpr(uint32_t sel)
|
||||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
|
||||
if (other_tc == other->current_tc)
|
||||
return other->active_tc.gpr[sel];
|
||||
|
|
@ -1798,7 +1798,7 @@ target_ulong helper_mftgpr(uint32_t sel)
|
|||
target_ulong helper_mftlo(uint32_t sel)
|
||||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
|
||||
if (other_tc == other->current_tc)
|
||||
return other->active_tc.LO[sel];
|
||||
|
|
@ -1809,7 +1809,7 @@ target_ulong helper_mftlo(uint32_t sel)
|
|||
target_ulong helper_mfthi(uint32_t sel)
|
||||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
|
||||
if (other_tc == other->current_tc)
|
||||
return other->active_tc.HI[sel];
|
||||
|
|
@ -1820,7 +1820,7 @@ target_ulong helper_mfthi(uint32_t sel)
|
|||
target_ulong helper_mftacx(uint32_t sel)
|
||||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
|
||||
if (other_tc == other->current_tc)
|
||||
return other->active_tc.ACX[sel];
|
||||
|
|
@ -1831,7 +1831,7 @@ target_ulong helper_mftacx(uint32_t sel)
|
|||
target_ulong helper_mftdsp(void)
|
||||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
|
||||
if (other_tc == other->current_tc)
|
||||
return other->active_tc.DSPControl;
|
||||
|
|
@ -1842,7 +1842,7 @@ target_ulong helper_mftdsp(void)
|
|||
void helper_mttgpr(target_ulong arg1, uint32_t sel)
|
||||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
|
||||
if (other_tc == other->current_tc)
|
||||
other->active_tc.gpr[sel] = arg1;
|
||||
|
|
@ -1853,7 +1853,7 @@ void helper_mttgpr(target_ulong arg1, uint32_t sel)
|
|||
void helper_mttlo(target_ulong arg1, uint32_t sel)
|
||||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
|
||||
if (other_tc == other->current_tc)
|
||||
other->active_tc.LO[sel] = arg1;
|
||||
|
|
@ -1864,7 +1864,7 @@ void helper_mttlo(target_ulong arg1, uint32_t sel)
|
|||
void helper_mtthi(target_ulong arg1, uint32_t sel)
|
||||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
|
||||
if (other_tc == other->current_tc)
|
||||
other->active_tc.HI[sel] = arg1;
|
||||
|
|
@ -1875,7 +1875,7 @@ void helper_mtthi(target_ulong arg1, uint32_t sel)
|
|||
void helper_mttacx(target_ulong arg1, uint32_t sel)
|
||||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
|
||||
if (other_tc == other->current_tc)
|
||||
other->active_tc.ACX[sel] = arg1;
|
||||
|
|
@ -1886,7 +1886,7 @@ void helper_mttacx(target_ulong arg1, uint32_t sel)
|
|||
void helper_mttdsp(target_ulong arg1)
|
||||
{
|
||||
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
||||
CPUState *other = mips_cpu_map_tc(&other_tc);
|
||||
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
|
||||
|
||||
if (other_tc == other->current_tc)
|
||||
other->active_tc.DSPControl = arg1;
|
||||
|
|
@ -1909,7 +1909,7 @@ target_ulong helper_emt(void)
|
|||
|
||||
target_ulong helper_dvpe(void)
|
||||
{
|
||||
CPUState *other_cpu = first_cpu;
|
||||
CPUMIPSState *other_cpu = first_cpu;
|
||||
target_ulong prev = env->mvp->CP0_MVPControl;
|
||||
|
||||
do {
|
||||
|
|
@ -1925,7 +1925,7 @@ target_ulong helper_dvpe(void)
|
|||
|
||||
target_ulong helper_evpe(void)
|
||||
{
|
||||
CPUState *other_cpu = first_cpu;
|
||||
CPUMIPSState *other_cpu = first_cpu;
|
||||
target_ulong prev = env->mvp->CP0_MVPControl;
|
||||
|
||||
do {
|
||||
|
|
@ -1981,14 +1981,14 @@ target_ulong helper_yield(target_ulong arg)
|
|||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
/* TLB management */
|
||||
static void cpu_mips_tlb_flush (CPUState *env, int flush_global)
|
||||
static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
|
||||
{
|
||||
/* Flush qemu's TLB and discard all shadowed entries. */
|
||||
tlb_flush (env, flush_global);
|
||||
env->tlb->tlb_in_use = env->tlb->nb_tlb;
|
||||
}
|
||||
|
||||
static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
|
||||
static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
|
||||
{
|
||||
/* Discard entries from env->tlb[first] onwards. */
|
||||
while (env->tlb->tlb_in_use > first) {
|
||||
|
|
@ -2316,11 +2316,11 @@ static void do_unaligned_access (target_ulong addr, int is_write, int is_user, v
|
|||
helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
||||
}
|
||||
|
||||
void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
|
||||
void tlb_fill(CPUMIPSState *env1, target_ulong addr, int is_write, int mmu_idx,
|
||||
void *retaddr)
|
||||
{
|
||||
TranslationBlock *tb;
|
||||
CPUState *saved_env;
|
||||
CPUMIPSState *saved_env;
|
||||
unsigned long pc;
|
||||
int ret;
|
||||
|
||||
|
|
@ -2343,7 +2343,7 @@ void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
|
|||
env = saved_env;
|
||||
}
|
||||
|
||||
void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
|
||||
void cpu_unassigned_access(CPUMIPSState *env1, target_phys_addr_t addr,
|
||||
int is_write, int is_exec, int unused, int size)
|
||||
{
|
||||
env = env1;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue