mirror of
https://github.com/Motorhead1991/qemu.git
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Initial support for Sun4d machines (SS-1000, SS-2000)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3869 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
8543e2cfce
commit
7d85892b9b
8 changed files with 455 additions and 16 deletions
278
hw/sun4m.c
278
hw/sun4m.c
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@ -1,5 +1,5 @@
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/*
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* QEMU Sun4m System Emulator
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* QEMU Sun4m & Sun4d System Emulator
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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@ -46,6 +46,11 @@
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* SPARCstation 20/xx, SPARCserver 20
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* SPARCstation 4
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*
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* Sun4d architecture was used in the following machines:
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*
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* SPARCcenter 2000
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* SPARCserver 1000
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*
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* See for example: http://www.sunhelp.org/faq/sunref1.html
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*/
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@ -86,6 +91,26 @@ struct hwdef {
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const char * const default_cpu_model;
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};
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#define MAX_IOUNITS 5
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struct sun4d_hwdef {
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target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
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target_phys_addr_t counter_base, nvram_base, ms_kb_base;
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target_phys_addr_t serial_base;
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target_phys_addr_t espdma_base, esp_base;
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target_phys_addr_t ledma_base, le_base;
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target_phys_addr_t tcx_base;
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target_phys_addr_t sbi_base;
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unsigned long vram_size, nvram_size;
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// IRQ numbers are not PIL ones, but SBI register bit numbers
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int esp_irq, le_irq, clock_irq, clock1_irq;
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int ser_irq, ms_kb_irq, me_irq;
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int machine_id; // For NVRAM
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uint32_t iounit_version;
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uint64_t max_mem;
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const char * const default_cpu_model;
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};
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/* TSC handling */
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uint64_t cpu_get_tsc()
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@ -122,7 +147,7 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
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const char *boot_devices, uint32_t RAM_size,
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uint32_t kernel_size,
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int width, int height, int depth,
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int machine_id)
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int machine_id, const char *arch)
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{
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unsigned int i;
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uint32_t start, end;
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@ -140,7 +165,7 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
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header->nvram_size = cpu_to_be16(0x2000);
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header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
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header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
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strcpy(header->arch, "sun4m");
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strcpy(header->arch, arch);
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header->nb_cpus = smp_cpus & 0xff;
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header->RAM0_base = 0;
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header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
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@ -203,12 +228,14 @@ static void *slavio_intctl;
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void pic_info()
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{
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slavio_pic_info(slavio_intctl);
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if (slavio_intctl)
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slavio_pic_info(slavio_intctl);
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}
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void irq_info()
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{
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slavio_irq_info(slavio_intctl);
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if (slavio_intctl)
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slavio_irq_info(slavio_intctl);
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}
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void cpu_check_irqs(CPUState *env)
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@ -488,7 +515,7 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
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nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
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boot_device, RAM_size, kernel_size, graphic_width,
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graphic_height, graphic_depth, hwdef->machine_id);
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graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
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if (hwdef->ecc_base != (target_phys_addr_t)-1)
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ecc_init(hwdef->ecc_base, hwdef->ecc_version);
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@ -716,3 +743,242 @@ QEMUMachine ss20_machine = {
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ss20_init,
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};
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static const struct sun4d_hwdef sun4d_hwdefs[] = {
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/* SS-1000 */
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{
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.iounit_bases = {
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0xfe0200000ULL,
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0xfe1200000ULL,
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0xfe2200000ULL,
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0xfe3200000ULL,
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-1,
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},
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.tcx_base = 0x820000000ULL,
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.slavio_base = 0xf00000000ULL,
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.ms_kb_base = 0xf00240000ULL,
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.serial_base = 0xf00200000ULL,
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.nvram_base = 0xf00280000ULL,
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.counter_base = 0xf00300000ULL,
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.espdma_base = 0x800081000ULL,
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.esp_base = 0x800080000ULL,
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.ledma_base = 0x800040000ULL,
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.le_base = 0x800060000ULL,
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.sbi_base = 0xf02800000ULL,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 3,
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.le_irq = 4,
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.clock_irq = 14,
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.clock1_irq = 10,
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.ms_kb_irq = 12,
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.ser_irq = 12,
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.machine_id = 0x80,
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.iounit_version = 0x03000000,
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.max_mem = 0xffffffff, // XXX actually first 62GB ok
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.default_cpu_model = "TI SuperSparc II",
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},
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/* SS-2000 */
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{
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.iounit_bases = {
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0xfe0200000ULL,
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0xfe1200000ULL,
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0xfe2200000ULL,
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0xfe3200000ULL,
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0xfe4200000ULL,
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},
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.tcx_base = 0x820000000ULL,
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.slavio_base = 0xf00000000ULL,
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.ms_kb_base = 0xf00240000ULL,
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.serial_base = 0xf00200000ULL,
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.nvram_base = 0xf00280000ULL,
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.counter_base = 0xf00300000ULL,
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.espdma_base = 0x800081000ULL,
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.esp_base = 0x800080000ULL,
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.ledma_base = 0x800040000ULL,
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.le_base = 0x800060000ULL,
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.sbi_base = 0xf02800000ULL,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 3,
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.le_irq = 4,
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.clock_irq = 14,
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.clock1_irq = 10,
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.ms_kb_irq = 12,
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.ser_irq = 12,
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.machine_id = 0x80,
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.iounit_version = 0x03000000,
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.max_mem = 0xffffffff, // XXX actually first 62GB ok
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.default_cpu_model = "TI SuperSparc II",
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},
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};
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static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, int RAM_size,
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const char *boot_device,
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DisplayState *ds, const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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CPUState *env, *envs[MAX_CPUS];
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unsigned int i;
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void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
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qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
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*espdma_irq, *ledma_irq;
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qemu_irq *esp_reset, *le_reset;
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unsigned long prom_offset, kernel_size;
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int ret;
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char buf[1024];
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int index;
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/* init CPUs */
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if (!cpu_model)
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cpu_model = hwdef->default_cpu_model;
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for (i = 0; i < smp_cpus; i++) {
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find Sparc CPU definition\n");
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exit(1);
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}
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cpu_sparc_set_id(env, i);
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envs[i] = env;
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if (i == 0) {
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qemu_register_reset(main_cpu_reset, env);
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} else {
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qemu_register_reset(secondary_cpu_reset, env);
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env->halted = 1;
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}
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register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
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cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
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env->prom_addr = hwdef->slavio_base;
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}
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for (i = smp_cpus; i < MAX_CPUS; i++)
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cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
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/* allocate RAM */
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if ((uint64_t)RAM_size > hwdef->max_mem) {
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fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
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(unsigned int)RAM_size / (1024 * 1024),
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(unsigned int)(hwdef->max_mem / (1024 * 1024)));
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exit(1);
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}
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cpu_register_physical_memory(0, RAM_size, 0);
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/* load boot prom */
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prom_offset = RAM_size + hwdef->vram_size;
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cpu_register_physical_memory(hwdef->slavio_base,
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(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
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TARGET_PAGE_MASK,
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prom_offset | IO_MEM_ROM);
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if (bios_name == NULL)
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bios_name = PROM_FILENAME;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
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ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
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if (ret < 0 || ret > PROM_SIZE_MAX)
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ret = load_image(buf, phys_ram_base + prom_offset);
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if (ret < 0 || ret > PROM_SIZE_MAX) {
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fprintf(stderr, "qemu: could not load prom '%s'\n",
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buf);
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exit(1);
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}
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/* set up devices */
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sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
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for (i = 0; i < MAX_IOUNITS; i++)
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if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
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iounits[i] = iommu_init(hwdef->iounit_bases[i], hwdef->iounit_version);
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espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
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iounits[0], &espdma_irq, &esp_reset);
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ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
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iounits[0], &ledma_irq, &le_reset);
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if (graphic_depth != 8 && graphic_depth != 24) {
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fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
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exit (1);
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}
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tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
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hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
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if (nd_table[0].model == NULL
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|| strcmp(nd_table[0].model, "lance") == 0) {
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lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
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} else if (strcmp(nd_table[0].model, "?") == 0) {
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fprintf(stderr, "qemu: Supported NICs: lance\n");
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exit (1);
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
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exit (1);
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}
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nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
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hwdef->nvram_size, 8);
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slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
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sbi_cpu_irq, smp_cpus);
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slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
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nographic);
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// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
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// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
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slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
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serial_hds[1], serial_hds[0]);
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if (drive_get_max_bus(IF_SCSI) > 0) {
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fprintf(stderr, "qemu: too many SCSI bus\n");
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exit(1);
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}
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main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq,
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esp_reset);
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for (i = 0; i < ESP_MAX_DEVS; i++) {
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index = drive_get_index(IF_SCSI, 0, i);
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if (index == -1)
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continue;
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esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
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}
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kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
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initrd_filename);
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nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
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boot_device, RAM_size, kernel_size, graphic_width,
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graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
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}
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/* SPARCserver 1000 hardware initialisation */
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static void ss1000_init(int RAM_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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/* SPARCcenter 2000 hardware initialisation */
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static void ss2000_init(int RAM_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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QEMUMachine ss1000_machine = {
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"SS-1000",
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"Sun4d platform, SPARCserver 1000",
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ss1000_init,
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};
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QEMUMachine ss2000_machine = {
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"SS-2000",
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"Sun4d platform, SPARCcenter 2000",
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ss2000_init,
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};
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