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hw/dma: Constify all Property

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-13 15:33:04 +00:00
parent d432edd56c
commit 7d6a82a3e6
7 changed files with 7 additions and 7 deletions
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2
hw/dma/i82374.c
View file

@ -139,7 +139,7 @@ static void i82374_realize(DeviceState *dev, Error **errp)
memset(s->commands, 0, sizeof(s->commands)); memset(s->commands, 0, sizeof(s->commands));
} }
static Property i82374_properties[] = { static const Property i82374_properties[] = {
DEFINE_PROP_UINT32("iobase", I82374State, iobase, 0x400), DEFINE_PROP_UINT32("iobase", I82374State, iobase, 0x400),
DEFINE_PROP_END_OF_LIST() DEFINE_PROP_END_OF_LIST()
}; };

2
hw/dma/i8257.c
View file

@ -585,7 +585,7 @@ static void i8257_realize(DeviceState *dev, Error **errp)
d->dma_bh = qemu_bh_new(i8257_dma_run, d); d->dma_bh = qemu_bh_new(i8257_dma_run, d);
} }
static Property i8257_properties[] = { static const Property i8257_properties[] = {
DEFINE_PROP_INT32("base", I8257State, base, 0x00), DEFINE_PROP_INT32("base", I8257State, base, 0x00),
DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80), DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80),
DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480), DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480),

2
hw/dma/pl080.c
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@ -408,7 +408,7 @@ static void pl081_init(Object *obj)
s->nchannels = 2; s->nchannels = 2;
} }
static Property pl080_properties[] = { static const Property pl080_properties[] = {
DEFINE_PROP_LINK("downstream", PL080State, downstream, DEFINE_PROP_LINK("downstream", PL080State, downstream,
TYPE_MEMORY_REGION, MemoryRegion *), TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),

2
hw/dma/pl330.c
View file

@ -1646,7 +1646,7 @@ static void pl330_realize(DeviceState *dev, Error **errp)
pl330_fifo_init(&s->fifo, s->data_width / 4 * s->data_buffer_dep); pl330_fifo_init(&s->fifo, s->data_width / 4 * s->data_buffer_dep);
} }
static Property pl330_properties[] = { static const Property pl330_properties[] = {
/* CR0 */ /* CR0 */
DEFINE_PROP_UINT32("num_chnls", PL330State, num_chnls, 8), DEFINE_PROP_UINT32("num_chnls", PL330State, num_chnls, 8),
DEFINE_PROP_UINT8("num_periph_req", PL330State, num_periph_req, 4), DEFINE_PROP_UINT8("num_periph_req", PL330State, num_periph_req, 4),

2
hw/dma/xilinx_axidma.c
View file

@ -611,7 +611,7 @@ static void xilinx_axidma_init(Object *obj)
sysbus_init_mmio(sbd, &s->iomem); sysbus_init_mmio(sbd, &s->iomem);
} }
static Property axidma_properties[] = { static const Property axidma_properties[] = {
DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000), DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA, DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA,
tx_data_dev, TYPE_STREAM_SINK, StreamSink *), tx_data_dev, TYPE_STREAM_SINK, StreamSink *),

2
hw/dma/xlnx-zdma.c
View file

@ -810,7 +810,7 @@ static const VMStateDescription vmstate_zdma = {
} }
}; };
static Property zdma_props[] = { static const Property zdma_props[] = {
DEFINE_PROP_UINT32("bus-width", XlnxZDMA, cfg.bus_width, 64), DEFINE_PROP_UINT32("bus-width", XlnxZDMA, cfg.bus_width, 64),
DEFINE_PROP_LINK("dma", XlnxZDMA, dma_mr, DEFINE_PROP_LINK("dma", XlnxZDMA, dma_mr,
TYPE_MEMORY_REGION, MemoryRegion *), TYPE_MEMORY_REGION, MemoryRegion *),

2
hw/dma/xlnx_csu_dma.c
View file

@ -691,7 +691,7 @@ static const VMStateDescription vmstate_xlnx_csu_dma = {
} }
}; };
static Property xlnx_csu_dma_properties[] = { static const Property xlnx_csu_dma_properties[] = {
/* /*
* Ref PG021, Stream Data Width: * Ref PG021, Stream Data Width:
* Data width in bits of the AXI S2MM AXI4-Stream Data bus. * Data width in bits of the AXI S2MM AXI4-Stream Data bus.