mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-03 15:53:54 -06:00
Patch queue for ppc - 2015-07-07
A few last minute PPC changes for 2.4: - spapr: Update SLOF - spapr: Fix a few bugs - spapr: Preparation for hotplug - spapr: Minor code cleanups - linux-user: Add mftb handling - kvm: Enable hugepage support with memory-backend-file - mac99: Remove nonexistent interrupt pin (Mac OS 9 fix) -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAABAgAGBQJVm/TZAAoJECszeR4D/txg0rUP/R1C5IAuY0vM7LOYRbp1jFmn EO6AZpJaXvT2xP0wUd/rqJct/O41vDVbEmnhpUAQwZcgsyw1UaKhRQbnCtY9PHD2 d7NZiBdv3AAbh8pLFadRjDJr/HrfuWVfjKKep5cM87/o3zjVreeIX8Hs77xHia6/ 90n3hcDF4QL8qx6fxCMT4mGpTtbxw85IcK2wyIU45cZSN0VYaTjDwcYokeSKqgxV pi7UjZSM5nZcn7VI1Uray4NkgXGs92Lorrbg08OFQt0AoXROJOk4V/LX3HkHfDbI BYUgaOQNdBkytkB3fJCsTgl2Up82bVP/tghMyZOIyBAU4MslnAOW6HAMX2TtNswx 7itnIb7DQsVDE/U234Xzf5qoH5x4nB9xKh2qLHPKSpgLChs6lAW37Af3N+V03JVb k/WX6i0n70a6kUqCxcMTnVSINWandU2jdJ/S8woIqs6XhfLk7hh0ucg+VhgoQxW7 QpeD69c25eVHeZDoMKR/ZTigJg/EQGuV9B9OSx6SyA9WMS4dImt1m0PBdaUlIAFT 759lMMwQIb5sQYghJ63tgrOI5PBneGnelM1zDWt2SCS0rbSjLWIWP47pHoNmnzzp vIhJX5GgVuzf0NrbZPSR7/6NuKKU6UW5CTGh3vFgRib/CWIbEgCE3yWQfflZKy5q Q2xBuAjyWnBoipzI4hlz =+Uma -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' into staging Patch queue for ppc - 2015-07-07 A few last minute PPC changes for 2.4: - spapr: Update SLOF - spapr: Fix a few bugs - spapr: Preparation for hotplug - spapr: Minor code cleanups - linux-user: Add mftb handling - kvm: Enable hugepage support with memory-backend-file - mac99: Remove nonexistent interrupt pin (Mac OS 9 fix) # gpg: Signature made Tue Jul 7 16:48:41 2015 BST using RSA key ID 03FEDC60 # gpg: Good signature from "Alexander Graf <agraf@suse.de>" # gpg: aka "Alexander Graf <alex@csgraf.de>" * remotes/agraf/tags/signed-ppc-for-upstream: (30 commits) sPAPR: Clear stale MSIx table during EEH reset sPAPR: Reenable EEH functionality on reboot sPAPR: Don't enable EEH on emulated PCI devices spapr-vty: Use TYPE_ definition instead of hardcoding spapr_vty: lookup should only return valid VTY objects spapr_pci: drop redundant args in spapr_[populate, create]_pci_child_dt spapr_pci: populate ibm,loc-code spapr_pci: enumerate and add PCI device tree xics_kvm: Don't enable KVM_CAP_IRQ_XICS if already enabled ppc: Update cpu_model in MachineState spapr: Consolidate cpu init code into a routine spapr: Reorganize CPU dt generation code cpus: Add a macro to walk CPUs in reverse spapr: Support ibm, lrdr-capacity device tree property spapr: Consider max_cpus during xics initialization Revert "hw/ppc/spapr_pci.c: Avoid functions not in glib 2.12 (g_hash_table_iter_*)" spapr_iommu: translate sPAPRTCEAccess to IOMMUAccessFlags spapr_iommu: drop erroneous check in h_put_tce_indirect() spapr_pci: set device node unit address as hex spapr_pci: encode class code including Prog IF register ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
7ce0f7dc87
31 changed files with 836 additions and 411 deletions
|
|
@ -119,21 +119,23 @@ struct sPAPRPHBVFIOState {
|
|||
|
||||
static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
|
||||
{
|
||||
sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
|
||||
|
||||
return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
|
||||
}
|
||||
|
||||
PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index);
|
||||
PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index);
|
||||
|
||||
int spapr_populate_pci_dt(sPAPRPHBState *phb,
|
||||
uint32_t xics_phandle,
|
||||
void *fdt);
|
||||
|
||||
void spapr_pci_msi_init(sPAPREnvironment *spapr, hwaddr addr);
|
||||
void spapr_pci_msi_init(sPAPRMachineState *spapr, hwaddr addr);
|
||||
|
||||
void spapr_pci_rtas_init(void);
|
||||
|
||||
sPAPRPHBState *spapr_pci_find_phb(sPAPREnvironment *spapr, uint64_t buid);
|
||||
PCIDevice *spapr_pci_find_dev(sPAPREnvironment *spapr, uint64_t buid,
|
||||
sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid);
|
||||
PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
|
||||
uint32_t config_addr);
|
||||
|
||||
#endif /* __HW_SPAPR_PCI_H__ */
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
#define __HW_SPAPR_H__
|
||||
|
||||
#include "sysemu/dma.h"
|
||||
#include "hw/boards.h"
|
||||
#include "hw/ppc/xics.h"
|
||||
#include "hw/ppc/spapr_drc.h"
|
||||
|
||||
|
|
@ -12,15 +13,42 @@ typedef struct sPAPRConfigureConnectorState sPAPRConfigureConnectorState;
|
|||
typedef struct sPAPREventLogEntry sPAPREventLogEntry;
|
||||
|
||||
#define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
|
||||
#define SPAPR_ENTRY_POINT 0x100
|
||||
|
||||
typedef struct sPAPRMachineClass sPAPRMachineClass;
|
||||
typedef struct sPAPRMachineState sPAPRMachineState;
|
||||
|
||||
#define TYPE_SPAPR_MACHINE "spapr-machine"
|
||||
#define SPAPR_MACHINE(obj) \
|
||||
OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
|
||||
#define SPAPR_MACHINE_GET_CLASS(obj) \
|
||||
OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE)
|
||||
#define SPAPR_MACHINE_CLASS(klass) \
|
||||
OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE)
|
||||
|
||||
/**
|
||||
* sPAPRMachineClass:
|
||||
*/
|
||||
struct sPAPRMachineClass {
|
||||
/*< private >*/
|
||||
MachineClass parent_class;
|
||||
|
||||
/*< public >*/
|
||||
};
|
||||
|
||||
/**
|
||||
* sPAPRMachineState:
|
||||
*/
|
||||
struct sPAPRMachineState {
|
||||
/*< private >*/
|
||||
MachineState parent_obj;
|
||||
|
||||
typedef struct sPAPREnvironment {
|
||||
struct VIOsPAPRBus *vio_bus;
|
||||
QLIST_HEAD(, sPAPRPHBState) phbs;
|
||||
struct sPAPRNVRAM *nvram;
|
||||
XICSState *icp;
|
||||
DeviceState *rtc;
|
||||
|
||||
hwaddr ram_limit;
|
||||
void *htab;
|
||||
uint32_t htab_shift;
|
||||
hwaddr rma_size;
|
||||
|
|
@ -29,7 +57,6 @@ typedef struct sPAPREnvironment {
|
|||
ssize_t rtas_size;
|
||||
void *rtas_blob;
|
||||
void *fdt_skel;
|
||||
target_ulong entry_point;
|
||||
uint64_t rtc_offset; /* Now used only during incoming migration */
|
||||
struct PPCTimebase tb;
|
||||
bool has_graphics;
|
||||
|
|
@ -46,7 +73,10 @@ typedef struct sPAPREnvironment {
|
|||
|
||||
/* RTAS state */
|
||||
QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list;
|
||||
} sPAPREnvironment;
|
||||
|
||||
/*< public >*/
|
||||
char *kvm_type;
|
||||
};
|
||||
|
||||
#define H_SUCCESS 0
|
||||
#define H_BUSY 1 /* Hardware busy -- retry later */
|
||||
|
|
@ -319,8 +349,6 @@ typedef struct sPAPREnvironment {
|
|||
#define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
|
||||
#define KVMPPC_HCALL_MAX KVMPPC_H_CAS
|
||||
|
||||
extern sPAPREnvironment *spapr;
|
||||
|
||||
typedef struct sPAPRDeviceTreeUpdateHeader {
|
||||
uint32_t version_id;
|
||||
} sPAPRDeviceTreeUpdateHeader;
|
||||
|
|
@ -335,7 +363,7 @@ typedef struct sPAPRDeviceTreeUpdateHeader {
|
|||
do { } while (0)
|
||||
#endif
|
||||
|
||||
typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
||||
typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
|
||||
target_ulong opcode,
|
||||
target_ulong *args);
|
||||
|
||||
|
|
@ -490,12 +518,12 @@ static inline void rtas_st_buffer(target_ulong phys, target_ulong phys_len,
|
|||
rtas_st_buffer_direct(phys + 2, phys_len - 2, buffer, buffer_len);
|
||||
}
|
||||
|
||||
typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
||||
typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
|
||||
uint32_t token,
|
||||
uint32_t nargs, target_ulong args,
|
||||
uint32_t nret, target_ulong rets);
|
||||
void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
|
||||
target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
||||
target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm,
|
||||
uint32_t token, uint32_t nargs, target_ulong args,
|
||||
uint32_t nret, target_ulong rets);
|
||||
int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
|
||||
|
|
@ -546,9 +574,10 @@ struct sPAPREventLogEntry {
|
|||
QTAILQ_ENTRY(sPAPREventLogEntry) next;
|
||||
};
|
||||
|
||||
void spapr_events_init(sPAPREnvironment *spapr);
|
||||
void spapr_events_init(sPAPRMachineState *sm);
|
||||
void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq);
|
||||
int spapr_h_cas_compose_response(target_ulong addr, target_ulong size);
|
||||
int spapr_h_cas_compose_response(sPAPRMachineState *sm,
|
||||
target_ulong addr, target_ulong size);
|
||||
sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn,
|
||||
uint64_t bus_offset,
|
||||
uint32_t page_shift,
|
||||
|
|
@ -578,4 +607,6 @@ void spapr_ccs_reset_hook(void *opaque);
|
|||
void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns);
|
||||
int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset);
|
||||
|
||||
#define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */
|
||||
|
||||
#endif /* !defined (__HW_SPAPR_H__) */
|
||||
|
|
|
|||
|
|
@ -88,6 +88,8 @@ extern int spapr_vio_signal(VIOsPAPRDevice *dev, target_ulong mode);
|
|||
|
||||
static inline qemu_irq spapr_vio_qirq(VIOsPAPRDevice *dev)
|
||||
{
|
||||
sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
|
||||
|
||||
return xics_get_qirq(spapr->icp, dev->irq);
|
||||
}
|
||||
|
||||
|
|
@ -126,7 +128,7 @@ static inline int spapr_vio_dma_set(VIOsPAPRDevice *dev, uint64_t taddr,
|
|||
|
||||
int spapr_vio_send_crq(VIOsPAPRDevice *dev, uint8_t *crq);
|
||||
|
||||
VIOsPAPRDevice *vty_lookup(sPAPREnvironment *spapr, target_ulong reg);
|
||||
VIOsPAPRDevice *vty_lookup(sPAPRMachineState *spapr, target_ulong reg);
|
||||
void vty_putchars(VIOsPAPRDevice *sdev, uint8_t *buf, int len);
|
||||
void spapr_vty_create(VIOsPAPRBus *bus, CharDriverState *chardev);
|
||||
void spapr_vlan_create(VIOsPAPRBus *bus, NICInfo *nd);
|
||||
|
|
|
|||
|
|
@ -109,6 +109,7 @@ struct ICPState {
|
|||
uint8_t pending_priority;
|
||||
uint8_t mfrr;
|
||||
qemu_irq output;
|
||||
bool cap_irq_xics_enabled;
|
||||
};
|
||||
|
||||
#define TYPE_ICS "ics"
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue