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RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3

Browse source 
This contains quite a few patches that I'd like to target for 4.2.
 They're mostly emulation fixes for the sifive_u board, which now much
 more closely matches the hardware and can therefor run the same fireware
 as what gets loaded onto the board.  Additional user-visible
 improvements include:
 
 * support for loading initrd files from the command line into Linux, via
   /chosen/linux,initrd-{start,end} device tree nodes.
 * The conversion of LOG_TRACE to trace events.
 * The addition of clock DT nodes for our uart and ethernet.
 
 This also includes some preliminary work for the H extension patches,
 but does not include the H extension patches as I haven't had time to
 review them yet.
 
 This passes my OE boot test on 32-bit and 64-bit virt machines, as well
 as a 64-bit upstream Linux boot on the sifive_u machine.  It has been
 fixed to actually pass "make check" this time.
 
 Changes since v2 (never made it to the list):
 
 * Sets the sifive_u machine default core count to 2 instead of 5.
 
 Changes since v1 <20190910190513.21160-1-palmer@sifive.com>:
 
 * Sets the sifive_u machine default core count to 5 instead of 1, as
   it's impossible to have a single core sifive_u machine.
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 YWJiZWx0LmNvbQAKCRDvTKFQLMurQTr/D/9HUJ7GKIrZ5j++RO47fy/IkJtv3Irb
 leOCGQdNBlyqiq9bPIQpcCprhpTDr7s0YyPzzztxWxAfpN3Pku2YgYhkOwiwCDPU
 5M55Zu8ppEBmU4Zh9p7A7ARbKEymBJ2ZwFxoKgXQ6bCzlmFdyHiA5tTfAxGEyRhB
 lt3u472DWMnfNakJp13CyLOM1FTDD6LyT8PDjpefCoWZWDU8gC2ALQHRLkdYeRYE
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Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-sf1-v3' into staging

RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3

This contains quite a few patches that I'd like to target for 4.2.
They're mostly emulation fixes for the sifive_u board, which now much
more closely matches the hardware and can therefor run the same fireware
as what gets loaded onto the board.  Additional user-visible
improvements include:

* support for loading initrd files from the command line into Linux, via
  /chosen/linux,initrd-{start,end} device tree nodes.
* The conversion of LOG_TRACE to trace events.
* The addition of clock DT nodes for our uart and ethernet.

This also includes some preliminary work for the H extension patches,
but does not include the H extension patches as I haven't had time to
review them yet.

This passes my OE boot test on 32-bit and 64-bit virt machines, as well
as a 64-bit upstream Linux boot on the sifive_u machine.  It has been
fixed to actually pass "make check" this time.

Changes since v2 (never made it to the list):

* Sets the sifive_u machine default core count to 2 instead of 5.

Changes since v1 <20190910190513.21160-1-palmer@sifive.com>:

* Sets the sifive_u machine default core count to 5 instead of 1, as
  it's impossible to have a single core sifive_u machine.

# gpg: Signature made Tue 17 Sep 2019 16:43:30 BST
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.2-sf1-v3: (48 commits)
  gdbstub: riscv: fix the fflags registers
  target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point
  target/riscv: Fix mstatus dirty mask
  target/riscv: Use both register name and ABI name
  riscv: sifive_u: Update model and compatible strings in device tree
  riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
  riscv: sifive_u: Fix broken GEM support
  riscv: sifive_u: Instantiate OTP memory with a serial number
  riscv: sifive: Implement a model for SiFive FU540 OTP
  riscv: roms: Update default bios for sifive_u machine
  riscv: sifive_u: Change UART node name in device tree
  riscv: sifive_u: Update UART base addresses and IRQs
  riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
  riscv: sifive_u: Add PRCI block to the SoC
  riscv: sifive_u: Generate hfclk and rtcclk nodes
  riscv: sifive: Implement PRCI model for FU540
  riscv: sifive_u: Update PLIC hart topology configuration string
  riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
  riscv: sifive_u: Set the minimum number of cpus to 2
  riscv: hart: Add a "hartid-base" property to RISC-V hart array
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-09-19 11:14:28 +01:00
commit 7cc0cdcd6a
41 changed files with 1366 additions and 444 deletions
Download patch file Download diff file Expand all files Collapse all files

1
include/hw/riscv/boot.h
View file

@ -25,6 +25,7 @@
void riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
hwaddr firmware_load_addr);
char *riscv_find_firmware(const char *firmware_filename);
target_ulong riscv_load_firmware(const char *firmware_filename,
hwaddr firmware_load_addr);
target_ulong riscv_load_kernel(const char *kernel_filename);

1
include/hw/riscv/riscv_hart.h
View file

@ -35,6 +35,7 @@ typedef struct RISCVHartArrayState {
/*< public >*/
uint32_t num_harts;
uint32_t hartid_base;
char *cpu_type;
RISCVCPU *harts;
} RISCVHartArrayState;

31
include/hw/riscv/sifive_cpu.h Normal file
View file

@ -0,0 +1,31 @@
/*
* SiFive CPU types
*
* Copyright (c) 2017 SiFive, Inc.
* Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_SIFIVE_CPU_H
#define HW_SIFIVE_CPU_H
#if defined(TARGET_RISCV32)
#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
#elif defined(TARGET_RISCV64)
#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
#endif
#endif /* HW_SIFIVE_CPU_H */

7
include/hw/riscv/sifive_e.h
View file

@ -20,6 +20,7 @@
#define HW_SIFIVE_E_H
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
#include "hw/riscv/sifive_gpio.h"
#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
@ -84,10 +85,4 @@ enum {
#define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000
#define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000
#if defined(TARGET_RISCV32)
#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
#elif defined(TARGET_RISCV64)
#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
#endif
#endif

71
include/hw/riscv/sifive_e_prci.h Normal file
View file

@ -0,0 +1,71 @@
/*
* QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface
*
* Copyright (c) 2017 SiFive, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_SIFIVE_E_PRCI_H
#define HW_SIFIVE_E_PRCI_H
enum {
SIFIVE_E_PRCI_HFROSCCFG = 0x0,
SIFIVE_E_PRCI_HFXOSCCFG = 0x4,
SIFIVE_E_PRCI_PLLCFG = 0x8,
SIFIVE_E_PRCI_PLLOUTDIV = 0xC
};
enum {
SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31),
SIFIVE_E_PRCI_HFROSCCFG_EN = (1 << 30)
};
enum {
SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31),
SIFIVE_E_PRCI_HFXOSCCFG_EN = (1 << 30)
};
enum {
SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16),
SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17),
SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18),
SIFIVE_E_PRCI_PLLCFG_LOCK = (1 << 31)
};
enum {
SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
};
#define SIFIVE_E_PRCI_REG_SIZE 0x1000
#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci"
#define SIFIVE_E_PRCI(obj) \
OBJECT_CHECK(SiFiveEPRCIState, (obj), TYPE_SIFIVE_E_PRCI)
typedef struct SiFiveEPRCIState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion mmio;
uint32_t hfrosccfg;
uint32_t hfxosccfg;
uint32_t pllcfg;
uint32_t plloutdiv;
} SiFiveEPRCIState;
DeviceState *sifive_e_prci_create(hwaddr addr);
#endif

3
include/hw/riscv/sifive_plic.h
View file

@ -69,9 +69,6 @@ typedef struct SiFivePLICState {
uint32_t aperture_size;
} SiFivePLICState;
void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq);
void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq);
DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
uint32_t num_sources, uint32_t num_priorities,
uint32_t priority_base, uint32_t pending_base,

71
include/hw/riscv/sifive_prci.h
View file

@ -1,71 +0,0 @@
/*
* QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface
*
* Copyright (c) 2017 SiFive, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_SIFIVE_PRCI_H
#define HW_SIFIVE_PRCI_H
#include "hw/sysbus.h"
enum {
SIFIVE_PRCI_HFROSCCFG = 0x0,
SIFIVE_PRCI_HFXOSCCFG = 0x4,
SIFIVE_PRCI_PLLCFG = 0x8,
SIFIVE_PRCI_PLLOUTDIV = 0xC
};
enum {
SIFIVE_PRCI_HFROSCCFG_RDY = (1 << 31),
SIFIVE_PRCI_HFROSCCFG_EN = (1 << 30)
};
enum {
SIFIVE_PRCI_HFXOSCCFG_RDY = (1 << 31),
SIFIVE_PRCI_HFXOSCCFG_EN = (1 << 30)
};
enum {
SIFIVE_PRCI_PLLCFG_PLLSEL = (1 << 16),
SIFIVE_PRCI_PLLCFG_REFSEL = (1 << 17),
SIFIVE_PRCI_PLLCFG_BYPASS = (1 << 18),
SIFIVE_PRCI_PLLCFG_LOCK = (1 << 31)
};
enum {
SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
};
#define TYPE_SIFIVE_PRCI "riscv.sifive.prci"
#define SIFIVE_PRCI(obj) \
OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_PRCI)
typedef struct SiFivePRCIState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion mmio;
uint32_t hfrosccfg;
uint32_t hfxosccfg;
uint32_t pllcfg;
uint32_t plloutdiv;
} SiFivePRCIState;
DeviceState *sifive_prci_create(hwaddr addr);
#endif

3
include/hw/riscv/sifive_test.h
View file

@ -36,7 +36,8 @@ typedef struct SiFiveTestState {
enum {
FINISHER_FAIL = 0x3333,
FINISHER_PASS = 0x5555
FINISHER_PASS = 0x5555,
FINISHER_RESET = 0x7777
};
DeviceState *sifive_test_create(hwaddr addr);

31
include/hw/riscv/sifive_u.h
View file

@ -21,6 +21,9 @@
#include "hw/net/cadence_gem.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
#include "hw/riscv/sifive_u_prci.h"
#include "hw/riscv/sifive_u_otp.h"
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
#define RISCV_U_SOC(obj) \
@ -31,8 +34,13 @@ typedef struct SiFiveUSoCState {
SysBusDevice parent_obj;
/*< public >*/
RISCVHartArrayState cpus;
CPUClusterState e_cluster;
CPUClusterState u_cluster;
RISCVHartArrayState e_cpus;
RISCVHartArrayState u_cpus;
DeviceState *plic;
SiFiveUPRCIState prci;
SiFiveUOTPState otp;
CadenceGEMState gem;
} SiFiveUSoCState;
@ -51,23 +59,30 @@ enum {
SIFIVE_U_MROM,
SIFIVE_U_CLINT,
SIFIVE_U_PLIC,
SIFIVE_U_PRCI,
SIFIVE_U_UART0,
SIFIVE_U_UART1,
SIFIVE_U_OTP,
SIFIVE_U_DRAM,
SIFIVE_U_GEM
SIFIVE_U_GEM,
SIFIVE_U_GEM_MGMT
};
enum {
SIFIVE_U_UART0_IRQ = 3,
SIFIVE_U_UART1_IRQ = 4,
SIFIVE_U_UART0_IRQ = 4,
SIFIVE_U_UART1_IRQ = 5,
SIFIVE_U_GEM_IRQ = 0x35
};
enum {
SIFIVE_U_CLOCK_FREQ = 1000000000,
SIFIVE_U_GEM_CLOCK_FREQ = 125000000
SIFIVE_U_HFCLK_FREQ = 33333333,
SIFIVE_U_RTCCLK_FREQ = 1000000
};
#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
#define SIFIVE_U_COMPUTE_CPU_COUNT 4
#define SIFIVE_U_PLIC_HART_CONFIG "MS"
#define SIFIVE_U_PLIC_NUM_SOURCES 54
#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
@ -78,10 +93,4 @@ enum {
#define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000
#define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
#if defined(TARGET_RISCV32)
#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
#elif defined(TARGET_RISCV64)
#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
#endif
#endif

80
include/hw/riscv/sifive_u_otp.h Normal file
View file

@ -0,0 +1,80 @@
/*
* QEMU SiFive U OTP (One-Time Programmable) Memory interface
*
* Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_SIFIVE_U_OTP_H
#define HW_SIFIVE_U_OTP_H
#define SIFIVE_U_OTP_PA 0x00
#define SIFIVE_U_OTP_PAIO 0x04
#define SIFIVE_U_OTP_PAS 0x08
#define SIFIVE_U_OTP_PCE 0x0C
#define SIFIVE_U_OTP_PCLK 0x10
#define SIFIVE_U_OTP_PDIN 0x14
#define SIFIVE_U_OTP_PDOUT 0x18
#define SIFIVE_U_OTP_PDSTB 0x1C
#define SIFIVE_U_OTP_PPROG 0x20
#define SIFIVE_U_OTP_PTC 0x24
#define SIFIVE_U_OTP_PTM 0x28
#define SIFIVE_U_OTP_PTM_REP 0x2C
#define SIFIVE_U_OTP_PTR 0x30
#define SIFIVE_U_OTP_PTRIM 0x34
#define SIFIVE_U_OTP_PWE 0x38
#define SIFIVE_U_OTP_PCE_EN (1 << 0)
#define SIFIVE_U_OTP_PDSTB_EN (1 << 0)
#define SIFIVE_U_OTP_PTRIM_EN (1 << 0)
#define SIFIVE_U_OTP_PA_MASK 0xfff
#define SIFIVE_U_OTP_NUM_FUSES 0x1000
#define SIFIVE_U_OTP_SERIAL_ADDR 0xfc
#define SIFIVE_U_OTP_REG_SIZE 0x1000
#define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp"
#define SIFIVE_U_OTP(obj) \
OBJECT_CHECK(SiFiveUOTPState, (obj), TYPE_SIFIVE_U_OTP)
typedef struct SiFiveUOTPState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion mmio;
uint32_t pa;
uint32_t paio;
uint32_t pas;
uint32_t pce;
uint32_t pclk;
uint32_t pdin;
uint32_t pdstb;
uint32_t pprog;
uint32_t ptc;
uint32_t ptm;
uint32_t ptm_rep;
uint32_t ptr;
uint32_t ptrim;
uint32_t pwe;
uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES];
/* config */
uint32_t serial;
} SiFiveUOTPState;
#endif /* HW_SIFIVE_U_OTP_H */

91
include/hw/riscv/sifive_u_prci.h Normal file
View file

@ -0,0 +1,91 @@
/*
* QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface
*
* Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_SIFIVE_U_PRCI_H
#define HW_SIFIVE_U_PRCI_H
#define SIFIVE_U_PRCI_HFXOSCCFG 0x00
#define SIFIVE_U_PRCI_COREPLLCFG0 0x04
#define SIFIVE_U_PRCI_DDRPLLCFG0 0x0C
#define SIFIVE_U_PRCI_DDRPLLCFG1 0x10
#define SIFIVE_U_PRCI_GEMGXLPLLCFG0 0x1C
#define SIFIVE_U_PRCI_GEMGXLPLLCFG1 0x20
#define SIFIVE_U_PRCI_CORECLKSEL 0x24
#define SIFIVE_U_PRCI_DEVICESRESET 0x28
#define SIFIVE_U_PRCI_CLKMUXSTATUS 0x2C
/*
* Current FU540-C000 manual says ready bit is at bit 29, but
* freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31.
* We have to trust the actual code that works.
*
* see https://github.com/sifive/freedom-u540-c000-bootloader
*/
#define SIFIVE_U_PRCI_HFXOSCCFG_EN (1 << 30)
#define SIFIVE_U_PRCI_HFXOSCCFG_RDY (1 << 31)
/* xxxPLLCFG0 register bits */
#define SIFIVE_U_PRCI_PLLCFG0_DIVR (1 << 0)
#define SIFIVE_U_PRCI_PLLCFG0_DIVF (31 << 6)
#define SIFIVE_U_PRCI_PLLCFG0_DIVQ (3 << 15)
#define SIFIVE_U_PRCI_PLLCFG0_FSE (1 << 25)
#define SIFIVE_U_PRCI_PLLCFG0_LOCK (1 << 31)
/* xxxPLLCFG1 register bits */
#define SIFIVE_U_PRCI_PLLCFG1_CKE (1 << 24)
/* coreclksel register bits */
#define SIFIVE_U_PRCI_CORECLKSEL_HFCLK (1 << 0)
#define SIFIVE_U_PRCI_REG_SIZE 0x1000
#define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci"
#define SIFIVE_U_PRCI(obj) \
OBJECT_CHECK(SiFiveUPRCIState, (obj), TYPE_SIFIVE_U_PRCI)
typedef struct SiFiveUPRCIState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion mmio;
uint32_t hfxosccfg;
uint32_t corepllcfg0;
uint32_t ddrpllcfg0;
uint32_t ddrpllcfg1;
uint32_t gemgxlpllcfg0;
uint32_t gemgxlpllcfg1;
uint32_t coreclksel;
uint32_t devicesreset;
uint32_t clkmuxstatus;
} SiFiveUPRCIState;
/*
* Clock indexes for use by Device Tree data and the PRCI driver.
*
* These values are from sifive-fu540-prci.h in the Linux kernel.
*/
#define PRCI_CLK_COREPLL 0
#define PRCI_CLK_DDRPLL 1
#define PRCI_CLK_GEMGXLPLL 2
#define PRCI_CLK_TLCLK 3
#endif /* HW_SIFIVE_U_PRCI_H */