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target/arm: Enable FEAT_CSV2_2 for -cpu max

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There is no branch prediction in TCG, therefore there is no
need to actually include the context number into the predictor.
Therefore all we need to do is add the state for SCXTNUM_ELx.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-05-06 13:02:38 -05:00 • committed by Peter Maydell
parent 74b17e1669
commit 7cb1e61851
5 changed files with 86 additions and 2 deletions
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61
target/arm/helper.c
View file

@ -1770,6 +1770,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
if (cpu_isar_feature(aa64_mte, cpu)) {
valid_mask |= SCR_ATA;
}
if (cpu_isar_feature(aa64_scxtnum, cpu)) {
valid_mask |= SCR_ENSCXT;
}
} else {
valid_mask &= ~(SCR_RW | SCR_ST);
if (cpu_isar_feature(aa32_ras, cpu)) {
@ -5149,6 +5152,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
if (cpu_isar_feature(aa64_mte, cpu)) {
valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
}
if (cpu_isar_feature(aa64_scxtnum, cpu)) {
valid_mask |= HCR_ENSCXT;
}
}
/* Clear RES0 bits. */
@ -5800,6 +5806,10 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
{ K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
"TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
{ K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
"SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
isar_feature_aa64_scxtnum },
/* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
/* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
};
@ -7223,7 +7233,52 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
},
};
#endif
static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
uint64_t hcr = arm_hcr_el2_eff(env);
int el = arm_current_el(env);
if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) {
if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) {
if (hcr & HCR_TGE) {
return CP_ACCESS_TRAP_EL2;
}
return CP_ACCESS_TRAP;
}
} else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
return CP_ACCESS_TRAP_EL2;
}
if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) {
return CP_ACCESS_TRAP_EL2;
}
if (el < 3
&& arm_feature(env, ARM_FEATURE_EL3)
&& !(env->cp15.scr_el3 & SCR_ENSCXT)) {
return CP_ACCESS_TRAP_EL3;
}
return CP_ACCESS_OK;
}
static const ARMCPRegInfo scxtnum_reginfo[] = {
{ .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
.access = PL0_RW, .accessfn = access_scxtnum,
.fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
{ .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
.access = PL1_RW, .accessfn = access_scxtnum,
.fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
{ .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
.access = PL2_RW, .accessfn = access_scxtnum,
.fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) },
{ .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
.access = PL3_RW,
.fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
};
#endif /* TARGET_AARCH64 */
static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
@ -8365,6 +8420,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
}
if (cpu_isar_feature(aa64_scxtnum, cpu)) {
define_arm_cp_regs(cpu, scxtnum_reginfo);
}
#endif
if (cpu_isar_feature(any_predinv, cpu)) {