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hw/intc/arm_gicv3_redist: Implement GICR_INMIR0
Add GICR_INMIR0 register and support access GICR_INMIR0. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-17-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2 changed files with 20 additions and 0 deletions
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@ -35,6 +35,15 @@ static int gicr_ns_access(GICv3CPUState *cs, int irq)
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return extract32(cs->gicr_nsacr, irq * 2, 2);
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return extract32(cs->gicr_nsacr, irq * 2, 2);
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}
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}
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static void gicr_write_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
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uint32_t *reg, uint32_t val)
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{
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/* Helper routine to implement writing to a "set" register */
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val &= mask_group(cs, attrs);
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*reg = val;
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gicv3_redist_update(cs);
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}
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static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
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static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
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uint32_t *reg, uint32_t val)
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uint32_t *reg, uint32_t val)
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{
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{
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@ -406,6 +415,10 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset,
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*data = value;
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*data = value;
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return MEMTX_OK;
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return MEMTX_OK;
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}
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}
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case GICR_INMIR0:
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*data = cs->gic->nmi_support ?
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gicr_read_bitmap_reg(cs, attrs, cs->gicr_inmir0) : 0;
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return MEMTX_OK;
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case GICR_ICFGR0:
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case GICR_ICFGR0:
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case GICR_ICFGR1:
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case GICR_ICFGR1:
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{
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{
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@ -555,6 +568,12 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
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gicv3_redist_update(cs);
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gicv3_redist_update(cs);
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return MEMTX_OK;
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return MEMTX_OK;
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}
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}
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case GICR_INMIR0:
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if (cs->gic->nmi_support) {
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gicr_write_bitmap_reg(cs, attrs, &cs->gicr_inmir0, value);
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}
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return MEMTX_OK;
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case GICR_ICFGR0:
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case GICR_ICFGR0:
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/* Register is all RAZ/WI or RAO/WI bits */
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/* Register is all RAZ/WI or RAO/WI bits */
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return MEMTX_OK;
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return MEMTX_OK;
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@ -110,6 +110,7 @@
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#define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04)
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#define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04)
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#define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00)
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#define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00)
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#define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00)
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#define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00)
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#define GICR_INMIR0 (GICR_SGI_OFFSET + 0x0F80)
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/* VLPI redistributor registers, offsets from VLPI_base */
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/* VLPI redistributor registers, offsets from VLPI_base */
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#define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70)
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#define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70)
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