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target/arm: Convert handle_rev to decodetree
This includes REV16, REV32, REV64. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-44-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
38f9950c8e
commit
7c6bdcdaed
2 changed files with 10 additions and 74 deletions
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@ -73,6 +73,7 @@
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@qrr_b . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=0
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@qrr_b . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=0
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@qrr_h . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=1
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@qrr_h . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=1
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@qrr_bh . q:1 ...... . esz:1 ...... ...... rn:5 rd:5 &qrr_e
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@qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e
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@qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e
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@qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0
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@qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0
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@ -1657,3 +1658,7 @@ CMGE0_v 0.10 1110 ..1 00000 10001 0 ..... ..... @qrr_e
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CMEQ0_v 0.00 1110 ..1 00000 10011 0 ..... ..... @qrr_e
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CMEQ0_v 0.00 1110 ..1 00000 10011 0 ..... ..... @qrr_e
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CMLE0_v 0.10 1110 ..1 00000 10011 0 ..... ..... @qrr_e
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CMLE0_v 0.10 1110 ..1 00000 10011 0 ..... ..... @qrr_e
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CMLT0_v 0.00 1110 ..1 00000 10101 0 ..... ..... @qrr_e
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CMLT0_v 0.00 1110 ..1 00000 10101 0 ..... ..... @qrr_e
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REV16_v 0.00 1110 001 00000 00011 0 ..... ..... @qrr_b
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REV32_v 0.10 1110 0.1 00000 00001 0 ..... ..... @qrr_bh
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REV64_v 0.00 1110 ..1 00000 00001 0 ..... ..... @qrr_e
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@ -8939,6 +8939,8 @@ TRANS(CMGE0_v, do_gvec_fn2, a, gen_gvec_cge0)
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TRANS(CMLT0_v, do_gvec_fn2, a, gen_gvec_clt0)
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TRANS(CMLT0_v, do_gvec_fn2, a, gen_gvec_clt0)
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TRANS(CMLE0_v, do_gvec_fn2, a, gen_gvec_cle0)
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TRANS(CMLE0_v, do_gvec_fn2, a, gen_gvec_cle0)
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TRANS(CMEQ0_v, do_gvec_fn2, a, gen_gvec_ceq0)
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TRANS(CMEQ0_v, do_gvec_fn2, a, gen_gvec_ceq0)
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TRANS(REV16_v, do_gvec_fn2, a, gen_gvec_rev16)
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TRANS(REV32_v, do_gvec_fn2, a, gen_gvec_rev32)
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static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
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static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
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{
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{
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@ -8953,6 +8955,7 @@ static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
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TRANS(CLS_v, do_gvec_fn2_bhs, a, gen_gvec_cls)
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TRANS(CLS_v, do_gvec_fn2_bhs, a, gen_gvec_cls)
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TRANS(CLZ_v, do_gvec_fn2_bhs, a, gen_gvec_clz)
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TRANS(CLZ_v, do_gvec_fn2_bhs, a, gen_gvec_clz)
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TRANS(REV64_v, do_gvec_fn2_bhs, a, gen_gvec_rev64)
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/* Common vector code for handling integer to FP conversion */
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/* Common vector code for handling integer to FP conversion */
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static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
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static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
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@ -9882,76 +9885,6 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
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}
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}
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}
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}
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static void handle_rev(DisasContext *s, int opcode, bool u,
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bool is_q, int size, int rn, int rd)
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{
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int op = (opcode << 1) | u;
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int opsz = op + size;
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int grp_size = 3 - opsz;
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int dsize = is_q ? 128 : 64;
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int i;
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if (opsz >= 3) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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if (size == 0) {
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/* Special case bytes, use bswap op on each group of elements */
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int groups = dsize / (8 << grp_size);
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for (i = 0; i < groups; i++) {
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TCGv_i64 tcg_tmp = tcg_temp_new_i64();
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read_vec_element(s, tcg_tmp, rn, i, grp_size);
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switch (grp_size) {
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case MO_16:
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tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp, TCG_BSWAP_IZ);
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break;
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case MO_32:
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tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp, TCG_BSWAP_IZ);
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break;
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case MO_64:
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tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp);
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break;
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default:
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g_assert_not_reached();
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}
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write_vec_element(s, tcg_tmp, rd, i, grp_size);
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}
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clear_vec_high(s, is_q, rd);
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} else {
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int revmask = (1 << grp_size) - 1;
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int esize = 8 << size;
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int elements = dsize / esize;
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TCGv_i64 tcg_rn = tcg_temp_new_i64();
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TCGv_i64 tcg_rd[2];
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for (i = 0; i < 2; i++) {
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tcg_rd[i] = tcg_temp_new_i64();
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tcg_gen_movi_i64(tcg_rd[i], 0);
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}
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for (i = 0; i < elements; i++) {
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int e_rev = (i & 0xf) ^ revmask;
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int w = (e_rev * esize) / 64;
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int o = (e_rev * esize) % 64;
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read_vec_element(s, tcg_rn, rn, i, size);
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tcg_gen_deposit_i64(tcg_rd[w], tcg_rd[w], tcg_rn, o, esize);
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}
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for (i = 0; i < 2; i++) {
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write_vec_element(s, tcg_rd[i], rd, i, MO_64);
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}
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clear_vec_high(s, true, rd);
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}
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}
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static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
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static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
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bool is_q, int size, int rn, int rd)
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bool is_q, int size, int rn, int rd)
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{
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{
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@ -10066,10 +9999,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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TCGv_ptr tcg_fpstatus;
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TCGv_ptr tcg_fpstatus;
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switch (opcode) {
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switch (opcode) {
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case 0x0: /* REV64, REV32 */
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case 0x1: /* REV16 */
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handle_rev(s, opcode, u, is_q, size, rn, rd);
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return;
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case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
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case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
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case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
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case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
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if (size == 3) {
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if (size == 3) {
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@ -10272,6 +10201,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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break;
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break;
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}
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}
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default:
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default:
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case 0x0: /* REV64, REV32 */
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case 0x1: /* REV16 */
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case 0x3: /* SUQADD, USQADD */
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case 0x3: /* SUQADD, USQADD */
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case 0x4: /* CLS, CLZ */
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case 0x4: /* CLS, CLZ */
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case 0x5: /* CNT, NOT, RBIT */
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case 0x5: /* CNT, NOT, RBIT */
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